參數(shù)資料
型號: 5V80001PGGI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: XO, clock
英文描述: 98.304 MHz, OTHER CLOCK GENERATOR, PDSO20
封裝: 4.40 MM, ROHS COMPLIANT, TSSOP-20
文件頁數(shù): 13/15頁
文件大?。?/td> 294K
代理商: 5V80001PGGI
IDT5V80001
MOST CLOCK INTERFACE
SYNTHESIZERS
IDT MOST CLOCK INTERFACE
7
IDT5V80001
REV S 083109
Timing Requirements
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Crystal Frequency
FIN
21.504
MHz
Input Rise Time
tR
S1=0, S0=0 (See Fig. 1)
10.0
ns
S1=0, S0=1 (See Fig. 1)
9.2
S1=1, S0=0 (See Fig. 1)
5.0
S1=1, S0=1 (See Fig. 1)
4.6
Input Fall Time
tF
S1=0, S0=0 (See Fig. 1)
10.0
ns
S1=0, S0=1 (See Fig. 1)
9.2
S1=1, S0=0 (See Fig. 1)
5.0
S1=1, S0=1 (See Fig. 1)
4.6
Input Pulse Width Variation
(FOT_IN and MOST_Din)
tPWV
S1=0, S0=0 (See Fig. 2)
16.4
31.1
ns
S1=0, S0=1 (See Fig. 2)
15.1
28.5
S1=1, S0=0 (See Fig. 2)
8.2
15.6
S1=1, S0=1 (See Fig. 2)
7.5
14.3
Average Input Pulse Width
Distortion
(FOT_IN and MOST_Din)
tAPWD
S1=0, S0=0 (See Fig. 2)
-3.4
+7.0
ns
S1=0, S0=1 (See Fig. 2)
-3.1
+6.5
S1=1, S0=0 (See Fig. 2)
-1.7
+3.5
S1=1, S0=1 (See Fig. 2)
-1.6
+3.3
One-Sigma Data
Dependent Jitter (FOT_IN)
tDDJ
S1=0, S0=0 (See Fig. 3)
0
3.4
ns
S1=0, S0=1 (See Fig. 3)
0
3.1
S1=1, S0=0 (See Fig. 3)
0
1.7
S1=1, S0=1 (See Fig. 3)
0
1.6
One-Sigma Uncorrelated
Jitter
tUJ
S1=0, S0=0 (See Fig. 4)
0
1000
ps
S1=0, S0=1 (See Fig. 4)
0
920
S1=1, S0=0 (See Fig. 4)
0
500
S1=1, S0=1 (See Fig. 4)
0
460
CDR Reset Time
tRESET
(see Fig. 5)
50
ns
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