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參數(shù)資料
| 型號(hào)： | 5V80001PGGI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | XO, clock |
| 英文描述： | 98.304 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| 封裝： | 4.40 MM, ROHS COMPLIANT, TSSOP-20 |
| 文件頁數(shù)： | 10/15頁 |
| 文件大?。?/td> | 294K |
| 代理商： | 5V80001PGGI |
IDT5V80001
MOST CLOCK INTERFACE
SYNTHESIZERS
IDT MOST CLOCK INTERFACE
4
IDT5V80001
REV S 083109
External Components
The IDT5V80001 requires a minimum number of external
components for proper operation.
Decoupling Capacitor
A decoupling capacitor of 0.01F must be connected
between each VDD pins and the ground plane, as close to
these pins as possible. For optimum device performance,
the decoupling capacitor should be mounted on the
component side of the PCB.
Crystal
The IDT5V80001 requires a 21.504 MHz parallel resonant
crystal. Recommended devices are:
Crystal Load Capacitors
The device crystal connections should include pads for
capacitors from X1 to ground and from X2 to ground. These
capacitors are used to adjust the stray capacitance of the
board to match the nominally required crystal load
capacitance.
The value (in pF) of these crystal caps should equal (CL -12
pF)*2. In this equation, CL= crystal load capacitance in pF.
For the specified 16 pF load capacitance, each crystal
capacitor would be 8 pF [(16-12) x 2 = 8].
External Loop Filter
An external loop filter is required for operation of the CDR
PLL. Recommended components are:
RS = 1210 , 1% tolerance
CS = 10 nF, use capacitor with a non-piezoelectric dielectric.
Recommended type is Panasonic ECH-U01103GX5 or
equivalent.
Series Termination Resistor
Termination should be used on the FOT_OUT, MCLK,
RCLK, and INPUT_COPY output (pins 5, 14, 16, and 18
respectively). To series terminate a 50
trace (a commonly
used trace impedance) place a 33
resistor in series with
the clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20
.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) The 0.01F decoupling capacitors should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via.
2) The external crystal should be mounted just next to the
device with short traces.
3) The external loop filter components should be mounted
close to the IDT5V80001 and away from digital signals,
switching power supply components, and other sources of
noise.
4) To minimize EMI, 33
series termination resistors should
be placed close to the clock outputs.
5) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers. Other signal traces should be routed away from the
IDT5V80001. This includes signal traces just underneath
the device, or on layers adjacent to the ground plane layer
used by the device.
External Loop Filter
Manufacturer
Package
Part #
Abracon
5x7 mm ceramic
AAH-363-21.504MHz
NDK
3.2x5 mm ceramic EXS00A-CG00294
9
10
11
12
R
S
C
S
LF
LFR
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參數(shù)描述 |
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| 5V80001PGGI8 | 制造商:Integrated Device Technology Inc 功能描述:PLL Frequency Synthesizer Dual 45.1584MHz to 98.304MHz 20-Pin TSSOP T/R 制造商:Integrated Device Technology Inc 功能描述:PLL FREQ SYNTHESIZER DUAL 45.1584MHZ TO 98.304MHZ 20TSSOP - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:MOST CLOCK INTERFACE |
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