VERSACLOCK LOW POWER CLOCK GENERATOR EEPROM CLOCK GENERATOR
參數(shù)資料
型號: 5P49EE801NDGI
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 19/27頁
文件大?。?/td> 0K
描述: IC CLOCK GENERATOR 28QFN
標準包裝: 75
系列: VersaClock™
類型: 時鐘發(fā)生器
PLL: 帶旁路
輸入: LVTTL,晶體
輸出: LVCMOS,LVDS,LVTTL
電路數(shù): 1
比率 - 輸入:輸出: 2:7
差分 - 輸入:輸出: 無/是
頻率 - 最大: 150MHz
除法器/乘法器: 是/無
電源電壓: 1.71 V ~ 1.89 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-VFQFN 裸露焊盤
供應商設備封裝: 28-VFQFPN(4x4)
包裝: 管件
其它名稱: 800-2524
IDT5P49EE801
VERSACLOCK LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
IDT VERSACLOCK LOW POWER CLOCK GENERATOR
26
IDT5P49EE801
REV M 072512
Revision History
Rev.
Date
Originator
Description of Change
--
9/23/09
R.Willner
Initial Preliminary Datasheet
A
11/20/09
R.Willner
No_PD bit inclusion - 32kHz clock on/off in Config 00.
B
3/25/10
R.Willner
Typographical changes. Correct spread spectrum calculations.
C
6/02/10
R.Willner
Typographical changes. Default configuration.
D
9/08/10
R.Willner
Input Clock max voltage swing 1.8V. Power ramp sequence.
E
10/29/10
R. Willner
Typographical changes. Loop filter calculations. Default register bit corrections.
F
01/19/11
R. Willner
Corrected notes on top-side marking.
G
04/13/11
R. Willner
1. Updated SCLK and SDA pin descriptions
2. Updated DC Electrical Char table for 1.8V LVTTL; added VIH and VIL.
3. Updated “Lock Time/PLL Lock Time from shutdown mode” Typ. and Max. specs in AC
Timing Electrical Char table.
H
05/04/11
R. Willner
Added Landing Pattern diagram.
J
08/24/11
R. Willner
Corrected SRC1 connections in block diagram.
K
0930/11
R. Willner
Updated Power-up/Power-down Sequence notes.
L
10/17/11
R. Willner
1. Added VDDOx specs to Recommended Operations table
2. Updated Power-up/down Sequence diagrams
M
07/25/12
R. Willner
Added pin 1 indicator dot on marking diagram.
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