VERSACLOCK LOW POWER CLOCK GENERATOR EEPROM CLOCK GENERATOR
參數(shù)資料
型號: 5P49EE801NDGI
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 16/27頁
文件大?。?/td> 0K
描述: IC CLOCK GENERATOR 28QFN
標(biāo)準(zhǔn)包裝: 75
系列: VersaClock™
類型: 時鐘發(fā)生器
PLL: 帶旁路
輸入: LVTTL,晶體
輸出: LVCMOS,LVDS,LVTTL
電路數(shù): 1
比率 - 輸入:輸出: 2:7
差分 - 輸入:輸出: 無/是
頻率 - 最大: 150MHz
除法器/乘法器: 是/無
電源電壓: 1.71 V ~ 1.89 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 28-VFQFPN(4x4)
包裝: 管件
其它名稱: 800-2524
IDT5P49EE801
VERSACLOCK LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
IDT VERSACLOCK LOW POWER CLOCK GENERATOR
23
IDT5P49EE801
REV M 072512
0x4F
00
OD3[7:0]
0x50
00
OD4[7:0]
0x51
00
OD5[7:0]
0x52
00
OD6[7:0]
0x53
00
SCR6[1:0]
SCR5[1:0]
SCR4[1:0]
SCR3[1:0]
0x54
00
Reserved
SCR2[1:0]
SCR1[1:0]
Reserved
0x55
01
SCR0[1:0]
Reserved
0x56
FF
Reserved
0x57
00
PDB[6]
LVDS_ON
OE[6B]
OE[6]
Reserved
0x58
00
OE[5]
OE[4]
OE[3]
Reserved
OE[2]
OE[1]
Reserved
OE[0]
0x59
00
PDB[5]
PDB[4]
PDB[3]
Reserved
PDB[2]
PDB[1]
Reserved
PDB[0]
0x5A
00
REFA[7:0]
Configuration2
(See definitions from Configuration0
above)
0x5B
00
FBA[10:3)
0x5C
00
Reserved
FBA[2:0)
0x5D
00
Reserved
XDIVA
RZA[1:0]
IPA[2:0]
REFSELA
0x5E
00
REFB[7:0]
0x5F
00
FBB[10:3]
0x60
00
MOD[4:0]
FBB[2:0]
0x61
00
MOD[12:5]
0x62
00
NC[10:3]
0x63
00
NSS[4:0]
NC[2:0]
0x64
00
NSS[12:5]
0x65
40
Reserved
IPB[2:0]
RZB[1:0]
0x66
00
Reserved
REFSELB
SSENB_B
0x67
00
REFC[7:0]
0x68
00
FBC[10:3]
0x69
00
Reserved
FBC[2:0]
0x6A
00
FBC2[7:0]
0x6B
00
IPC[2:0]
RZC[1:0]
Reserved
XDIV
REFSELC
0x6C
00
REFD[7:0]
0x6D
00
FBD[10:3]
0x6E
00
Reserved
FBD[2:0]
0x6F
00
XDIVD
RZD[1:0]
IPD[2:0]
REFSELD[1:0]
0x70
00
OD0[7:0]
0x71
00
Reserved
0x72
00
OD1[7:0]
0x73
00
OD2[7:0]
0x74
00
Reserved
0x75
00
OD3[7:0]
0x76
00
OD4[7:0]
0x77
00
OD5[7:0]
0x78
00
OD6[7:0]
0x79
00
SCR6[1:0]
SCR5[1:0]
SCR4[1:0]
SCR3[1:0]
0x7A
00
Reserved
SCR2[1:0]
SCR1[1:0]
Reserved
0x7B
01
SCR0[1:0]
Reserved
0x7C
FF
Reserved
0x7D
00
PDB[6]
LVDS_ON
OE[6B]
OE[6]
Reserved
0x7E
00
OE[5]
OE[4]
OE[3]
Reserved
OE[2]
OE[1]
Reserved
OE[0]
0x7F
00
PDB[5]
PDB[4]
PDB[3]
Reserved
PDB[2]
PDB[1]
Reserved
PDB[0]
Addr
Default
Register
Hex
Value
Bit #
Description
76
5
4
3
2
1
0
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