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參數(shù)資料
| 型號(hào)： | 5962R9572201VQC |
| 廠商： | INTERSIL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 5 MHz, MICROPROCESSOR, CDIP40 |
| 封裝： | CERAMIC, DIP-40 |
| 文件頁數(shù)： | 5/29頁 |
| 文件大小： | 322K |
| 代理商： | 5962R9572201VQC |
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13
FIGURE 3. BUS TIMING - MAXIMUM MODE SYSTEM
NOTES:
51. All signals switch between VOH and VOL unless otherwise specified.
52. RDY is sampled near the end of T2, T3, TW to determine if TW machines states are to be inserted.
53. Cascade address is valid between first and second INTA cycle.
54. Two INTA cycles run back-to-back. The HS-80C86RH local ADDR/DATA bus is inactive during both INTA cycles. Control for pointer address is
shown for the second INTA cycle.
55. Signals at HS-82C85RH or 82C88 are shown for reference only.
56. The issuance of the 82C88 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA and DEN) lags the active high
82C88 CEN.
57. All timing measurements are made at 1.5V unless otherwise noted.
58. Status inactive in state just prior to T4.
Waveforms (Continued)
T1
T2
T3
T4
TCLCL
TCH1CH2
TCL2CL1 TW
TCHCL
TCLCH
TCHSV
TCLSH
(SEE NOTE 58)
TCLDV
TCLAX
TCLAV
BHE, A19-A16
TSVLH
TCLLH
TR1VCL
TCHLL
TRYLCL
TCLR1X
TCLAV
TRYHCH
TDVCL
TCLDX1
TCLAX
AD15-AD0
DATA IN
TRYHSH
TCLRH
TRHAV
TCHDTL
TCLRL
TRLRH
TCHDTH
TAZRL
TCLML
TCLMH
TCVNV
TCVNX
TCLAZ
CLK
QS0, QS1
S2, S1, S0 (EXCEPT HALT)
BHE/S7, A19/S6-A16/S3
ALE (82C88 OUTPUT)
RDY
(HS-82C85RH INPUT)
NOTE 55
READY (HS-80C86RH INPUT)
READ CYCLE
82C88
OUTPUTS
SEE NOTES
55, 56
MRDC OR IORC
DEN
S7-S3
AD15-AD0
RD
DT/R
TCLAV
TCHRYX
HS-80C86RH
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| 5962R9583301VFA | 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵(lì)器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
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