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參數(shù)資料
| 型號： | 5962R9572201VQC |
| 廠商： | INTERSIL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 5 MHz, MICROPROCESSOR, CDIP40 |
| 封裝： | CERAMIC, DIP-40 |
| 文件頁數(shù)： | 25/29頁 |
| 文件大小： | 322K |
| 代理商： | 5962R9572201VQC |
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5
NMI
17
I
NON-MASKABLE INTERRUPT: is an edge triggered input which causes a type 2 interrupt. An interrupt
service routine is called via an interrupt vector lookup table located in system memory. NMI is not
maskable internally by software. A transition from LOW to HIGH initiates the interrupt at the end of the
current instruction. This input is internally synchronized.
RESET
21
I
RESET: causes the processor to immediately terminate its present activity. The signal must change from
LOW to HIGH and remain active HIGH for at least 4 CLK cycles. It restarts execution, as described in the
Instruction Set description, when RESET returns LOW. RESET is internally synchronized.
CLK
19
I
CLOCK: provides the basic timing for the processor and bus controller. It is asymmetric with a 33% duty
cycle to provide optimized internal timing.
VDD
40
VDD: +5V power supply pin. A 0.1
F capacitor between pins 20 and 40 is recommended for decoupling.
GND
1, 20
GND: Ground. Note: both must be connected. A 0.1
F capacitor between pins 1 and 20 is
recommended for decoupling.
MN/MX
33
I
MINIMUM/MAXIMUM: Indicates what mode the processor is to operate in. The two modes are discussed
in the following sections.
The following pin function descriptions are for the HS-80C86RH system in maximum mode (i.e., MN/MX = GND). Only the pin functions which are
unique to maximum mode are described below.
S0, S1, S2
26-28
O
STATUS: is active during T4, T1 and T2 and is returned to the passive state (1,1,1) during T3 or during
TW when READY is HIGH. This status is used by the 82C88 Bus Controller to generate all memory and
I/O access control signals. Any change by S2, S1, or S0 during T4 is used to indicate the beginning of a
bus cycle, and the return to the passive state in T3 or TW is used to indicate the end of a bus cycle. These
status lines are encoded. These signals are held at a high impedance logic one state during “grant
sequence”.
S2
S1
S0
0
Interrupt Acknowledge
0
1
Read I/O Port
0
1
0
Write I/O Port
0
1
Halt
1
0
Code Access
1
0
1
Read Memory
1
0
Write Memory
1
Passive
Pin Descriptions (Continued)
SYMBOL
PIN
NUMBER
TYPE
DESCRIPTION
HS-80C86RH
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 5962R9572701VXC | 制造商:Harris Corporation 功能描述: |
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| 5962R9578201VCC | 制造商:Harris Corporation 功能描述: |
| 5962R9581401VXC | 制造商:Harris Corporation 功能描述: |
| 5962R9583301VFA | 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
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