參數(shù)資料
型號: 5962R0521402VXC
元件分類: 時鐘產(chǎn)生/分配
英文描述: 200 MHz, OTHER CLOCK GENERATOR, CDFP48
封裝: CERAMIC, DFP-48
文件頁數(shù): 23/23頁
文件大?。?/td> 174K
代理商: 5962R0521402VXC
9
IN
DEVELOPMENT
4PD/DIV
I
3-Level
Power down and reference divider control. This dual function pin controls the
power down operation and selects the input reference divider. The following table
summarizes the operating states controlled by the PD/DIV pin.
PD/DIV
Operating Mode
Input Reference Divider
LOW
Powered Down
N/A
MID
Normal Operation
÷ 2
HIGH
Normal Operation
÷ 1
20
LOCK
O
LVTTL
PLL lock indication signal. A HIGH state indicates that the PLL is in a locked
condition. A LOW state indicates that the PLL is not locked and the outputs may
not be synchronized to the input. As the following table indicates, the level of phase
alignment between XTAL1 and FB that will cause the LOCK pin to change states is
dependent upon the frequency range selected by the FS input.
FS
LOCK Resolution
L
1.6ns typical
M
1.6ns typical
H
800ps typical
** Note: When the RadClock is in a power-down mode or the reference clock is
removed, the LOCK pin will transition to its HIGH state.
43
VDDQ4
2
PWR
Power
Power supply for Bank 4 output buffers.
Please see Table 12 for supply level constraints.
7
VDDQ3
2
PWR
Power
Power supply for Bank 3output buffers.
Please see Table 12 for supply level constraints.
19, 30
VDDQ1
2
PWR
Power
Power supply for Bank 1 and Bank 2 output buffers.
Please see Table 12 for supply level constraints.
6, 12, 14,
35, 38
VDD
2
PWR
Power
Power supply for internal circuitry.
Please see Table 12 for supply level constraints.
10, 11, 15,
16, 21, 29,
33, 34, 39,
40, 44, 45
VSS
PWR
Power
Ground
Flatpack
Pin No.
Name
I/O
Type
Description
Notes:
1. When TEST = MID and sOE = HIGH, the PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew
selections remain in effect unless nF[1:0] = LL.
2. A bypass capacitor (0.1
F) should be placed as close as possible to each positive power pin (<0.2"). An additional 1F capacitor should be located within 0.2"
of the output bank power supplies (VDDQ1, VDDQ3, and VDDQ4). If these bypass capacitors are not close to the pins, their high frequency filtering character-
istics will be cancelled by the parasitic inductance of the traces. Additionally, it is recommend that wide traces (0.025" or wider) be used when connecting the
decoupling capacitors to their respective power pins on the RadClock.
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