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參數(shù)資料
| 型號(hào)： | 5962R0521402VXC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 200 MHz, OTHER CLOCK GENERATOR, CDFP48 |
| 封裝： | CERAMIC, DFP-48 |
| 文件頁數(shù)： | 20/23頁 |
| 文件大小： | 174K |
| 代理商： | 5962R0521402VXC |
6
IN
DEVELOPMENT
When the outputs are configured for low drive operation, they
will provide a minimum 12mA of drive current regardless of
the selected output power supply. If the outputs are configured
for high drive operation, they will provide a minimum 24mA of
drive current under a 3.3V power supply and 20mA when pow-
ered from a 2.5V supply.
The UT7R995/C features split power supply buses for Banks 1
and 2, Bank 3, and Bank 4. These independent power supplies
enable the user to obtain both 3.3V and 2.5V output signals
from one UT7R995/C device. The core power supply (VDD)
must run from a 3.3V power supply. Table 12 summarizes the
various power supply options available with the UT7R995/C.
Notes:
1. VDDQ1/3/4 must not be set at a level higher than that of VDD.
1.4 Reference Clock Interfaces
When an external, LVCMOS/LVTTL, digital clock is used to
drive the UT7R995 and UT7R995C, the reference clock signal
should drive the XTAL1 input of the RadClock, while the
XTAL2 output should be left unconnected (see Figure 4). Note,
for the UT7R995 only, the XTAL2 pin is defined as a no-con-
nect.
In addition to a digital clock reference, the UT7R995C can in-
terface to a quartz crystal. When interfacing to a quartz crystal,
XTAL1 and XTAL2 are the input and output, respectively, of
an inverting amplifier within the RadClock. This inverting am-
plifier provides the initial 180o phase shift of the reference
clock whose frequency, and subsequent 180o phase shift, is set
by the quartz crystal and its surrounding RLC network. Figure
5 shows a typical pierce-oscillator with tank-circuit that will
support reliable startup of fundamental and odd-harmonic, AT-
cut, quartz crystals.
Table 12: Power Supply Constraints 1
VDD
VDDQ1
VDDQ3
VDDQ4
3.3V
3.3V or 2.5V
N/C
External
Digital
Oscillator
NC/XTAL2
XTAL1
VSS
Figure 4. External Digital Clock Oscillator Interface
Figure 5. Pierce Crystal Oscillator with Tank Circuit
Y1
Rdc
R1
C1
C2
L1
Cdc
XTAL1
XTAL2
UT7R995C
Fundamental Frequency Pierce Crystal Oscillator
Rdc = ~10M
;
L1 = Not Used;
Cdc = Not Used
C2 is used to tune the circuit for stable oscillation.
Typical values for C2 range from 30pF to 50pF.
R1 and C1 are selected to create a time constant that facilitates the funda-
mental frequency (fF) of the quartz crystal as defined in equation 2.
As an example, selecting a value of 100
for R1 and 80pF for C1 would fa-
cilitate the reliable operation of a 20MHz, AT-cut, quartz crystal.
Higher Frequency Pierce Crystal Oscillator
Rdc = ~10M
;
Cdc = ~1.5nF;
C2 = Tuning capacitor
similar to prior example
R1 and C1 are selected to create a time constant that facilitates the overtone
frequency (fOT) of the quartz crystal as shown in equation 3.
Additionally, L1 is selected such that its relationship with C2 facilitates a
frequency falling between the fundamental frequency (fF) and the specified
overtone frequency (fOT) of the quartz crystal as shown in equation 4.
As an example, selecting the following component values will result in a
50MHz Pierce Crystal Oscillator based upon an 3rd overtone, AT-cut,
quartz crystal having a fundamental frequency of 16.6666MHz.
Rdc = 10MW;
Cdc = 1.5nF;
C2 = 30pF;
R1 = 50W;
C1 = 55pF;
L1 = 300nH
fF = 16.6666MHz;
fOT = 50MHz
()1
*
1
*
2
1
C
R
f
F
π
=
Equation 2.
Equation 3.
()1
*
1
*
2
1
C
R
f
OT
π
=
()
1
*
1
*
2
1
C
L
f
M
π
=
Equation 4.
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