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參數(shù)資料
| 型號： | 5962G9855201QXX |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 12 MHz, RISC MICROCONTROLLER, CPGA144 |
| 封裝： | CERAMIC, PGA-144 |
| 文件頁數(shù)： | 63/64頁 |
| 文件大?。?/td> | 1464K |
| 代理商： | 5962G9855201QXX |
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8
UART Receiver Register (RCVR)
The UART Receiver Buffer Register (see figure 7) receives
9600-baud asynchronous serial data through the UARTIN
input pin on the UT69R000. Each serial data string contains an
active-low Start bit, eight Data bits, an odd Parity bit, and an
active-high Stop bit. Figure 8 shows a single serial data string.
While receiving a serial data string, the UT69R000 generates
four status flags: Data Ready (DR), Overrun Error (OE),
Framing Error (FE), and Parity Error (PE). The UT69R000
stores these bits in the System Status Register.
Receiver buffer register bits 15-8 are always low. Bit numbers,
7 to 0 (RCD7 - RCD0) contain data the UT69R000 receives
via the serial data port. RCD7 is the MSB; RCD0 is the LSB.
Bit 5
FE
Framing Error. When active, this bit indicates a stop bit was
missing from the serial transmission string. Cleared on next
transmission. [0]
Bit 4
PE
Parity Error. When active, this bit indicates the serial
transmission was received with the incorrect parity. Cleared
on next transmission. [0]
Bit 3
CN
Discrete Input 2. This bit reflects the input stimulus applied
to the input pin.
Bit 2
TBE
UART Transmitter Buffer Empty. This bit indicates the
Transmitter Buffer Register is empty and ready for data. [0]
Bit 1
TE
UART Transmitter Empty. This bit is low while the UART is
transmitting data and goes high when the transmission is
complete. [0]
Bit 0
DR
UART Data Ready. This active-high signal indicates the
UART received a serial data word and this data is available.
Cleared on the execution of INR Rd, RCVR. [0]
Bit Number
Mnemonic
Description
15 14 13 12 11 10 9
8
7
5
4
3 2
1 0
05
04
03
02
01
00
7
06
0
6
R
C
D
R
C
D
R
C
D
R
C
D
R
C
D
R
C
D
R
C
D
R
C
D
MSB
LSB
Figure 7. The UART Receiver
Buffer Register (RCVR)
5
4
T3
R
2
01
S
T
D
7
R
C
D
R
C
D
R
C
6
R
C
D
R
C
D
R
C
D
R
C
D
R
C
D
P
A
S
T
O
Figure 8. UART Receiver Single Serial
Data String
P
R
DATA
FLOW
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