參數(shù)資料
型號(hào): 5962G9855201QXX
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 12 MHz, RISC MICROCONTROLLER, CPGA144
封裝: CERAMIC, PGA-144
文件頁數(shù): 10/64頁
文件大?。?/td> 1464K
代理商: 5962G9855201QXX
18
3.1.2 LRI Instruction Bus Cycle
During an LRI instruction, the UT69R000 moves the
instruction data from the instruction memory to the
UT69R000.Figure 19 shows the timing diagram of the signal
relationships for the UT69R000 during an LRI Instruction Bus
Cycle.
Just as with the STRI instruction, before the UT69R000
executes the LRI instruction the system programmer must load
the UT69R000’s accumulator with the address from which the
data will be read. After the ACC is loaded with the address
information, LRI instruction execution can take place.
OSCIN
CK1
CK2
CK3
CK4
Figure 16. Machine Cycle 2 (3 Clock Cycle Instructions)
STATE1
EXECUTE
FETCH
RA(19:0)
RD(15:0)
Note:
1. Examples of three clock cycle instructions include (operand port accesses):
LR Rd, Rs
STR Rd, Rs
STATUS
DS
A(15:0)
D(15:0)
Address Valid
Data Read
Control Valid
Fetch Address Valid
Fetch Instruction
Fetch Address Valid
Fetch Instruction
(M/IO, R/WR)
相關(guān)PDF資料
PDF描述
5962G9855202VXA 32-BIT, 16 MHz, RISC MICROCONTROLLER, CPGA144
5962G9855202VXX 32-BIT, 16 MHz, RISC MICROCONTROLLER, CPGA144
5962H9855201VXC 32-BIT, 12 MHz, RISC MICROCONTROLLER, CPGA144
5962H9855202QXX 32-BIT, 16 MHz, RISC MICROCONTROLLER, CPGA144
5962H9855202VXX 32-BIT, 16 MHz, RISC MICROCONTROLLER, CPGA144
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