參數(shù)資料
型號(hào): 5962-9205803MYA
廠商: TEXAS INSTRUMENTS INC
元件分類: 數(shù)字信號(hào)處理
英文描述: 32-BIT, 40 MHz, OTHER DSP, CQFP132
封裝: NON CONDUCTIVE TIE BAR, CERAMIC, QFP-132
文件頁(yè)數(shù): 54/54頁(yè)
文件大小: 1033K
代理商: 5962-9205803MYA
SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026G APRIL 1998 REVISED SEPTEMBER 2006
9
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
functional block diagram
24
Boot
Loader
Cache
(64
× 32)
RAM
Block 0
(1K
× 32)
RAM
Block 1
(1K
× 32)
RDY
HOLD
HOLDA
STRB
R/ W
D31 D0
A23 A0
RESET
IR
PC
CPU1
REG1
REG2
MUX
40
32
24
BK
ARAU0
ARAU1
DISP0, IR0, IR1
Extended-
Precision
Registers
(R7R0)
Auxiliary
Registers
(AR0 AR7)
Other
Registers
(12)
40
Multiplier
32-Bit
Barrel
Shifter
ALU
DMA Controller
Global-Control
Register
Source-Address
Register
Destination-
Address
Register
Serial Port 0
Serial-Port-Control
Register
Receive/Transmit
(R / X) Timer Register
Data-Transmit
Register
Data-Receive
Register
FSX0
DX0
CLKX0
FSR0
DR0
CLKR0
Timer 0
Global-Control
Register
Timer-Period
Register
Timer-Counter
Register
TCLK0
Timer 1
Global-Control
Register
Timer-Period
Register
Timer-Counter
Register
TCLK1
Port Control
STRB-Control
Register
Transfer-
Counter
Register
PDATA Bus
PADDR Bus
DDATA Bus
DADDR1 Bus
DADDR2 Bus
DMADATA Bus
DMAADDR Bus
24
40
32
24
32
INT(3 0)
IACK
MCBL / MP
XF(1,0)
VDD(19 0)
VSS(24 0)
X1
X2 / CLKIN
H1
H3
EMU(3 0)
32
24
32
CPU2
32
40
MUX
Controller
Peripheral
Data
Bus
Peripheral
Address
Bus
CPU1
REG1
REG2
MUX
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