參數(shù)資料
型號(hào)： 5962-9205803MYA
廠商： TEXAS INSTRUMENTS INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 32-BIT, 40 MHz, OTHER DSP, CQFP132
封裝： NON CONDUCTIVE TIE BAR, CERAMIC, QFP-132
文件頁數(shù)： 29/54頁
文件大?。?/td> 1033K
代理商： 5962-9205803MYA
SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026G APRIL 1998 REVISED SEPTEMBER 2006
35
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
serial-port timing for SMJ320C31-50 (see Figure 26 and Figure 27)
NO.
’C31-50
UNIT
NO.
MIN
MAX
UNIT
54
td(H1H-SCK)
Delay time, H1 high to internal CLKX/R
10
ns
55
tc(SCK)
Cycle time, CLKX/R
CLKX/R ext
tc(H)x2.6
ns
55
tc(SCK)
Cycle time, CLKX/R
CLKX/R int
tc(H)x2
tc(H)x232
ns
56
tw(SCK)
Pulse duration, CLKX/R high/low
CLKX/R ext
tc(H)+10
ns
56
tw(SCK)
Pulse duration, CLKX/R high/low
CLKX/R int
[tc(SCK)/2]5
[tc(SCK)/2]+5
ns
57
tr(SCK)
Rise time, CLKX/R
6
ns
58
tf(SCK)
Fall time, CLKX/R
6
ns
59
td(C-DX)
Delay time, CLKX to DX valid
CLKX ext
24
ns
59
td(C-DX)
Delay time, CLKX to DX valid
CLKX int
16
ns
60
tsu(DR-CLKRL)
Setup time, DR before CLKR low
CLKR ext
9
ns
60
tsu(DR-CLKRL)
Setup time, DR before CLKR low
CLKR int
17
ns
61
th(CLKRL-DR)
Hold time, DR from CLKR low
CLKR ext
7
ns
61
th(CLKRL-DR)
Hold time, DR from CLKR low
CLKR int
0
ns
62
td(C-FSX)
Delay time, CLKX to internal FSX high/low
CLKX ext
22
ns
62
td(C-FSX)
Delay time, CLKX to internal FSX high/low
CLKX int
15
ns
63
tsu(FSR-CLKRL)
Setup time, FSR before CLKR low
CLKR ext
7
ns
63
tsu(FSR-CLKRL)
Setup time, FSR before CLKR low
CLKR int
7
ns
64
th(SCKL-FS)
Hold time, FSX/R input from CLKX/R low
CLKX/R ext
7
ns
64
th(SCKL-FS)
Hold time, FSX/R input from CLKX/R low
CLKX/R int
0
ns
65
tsu(FSX-C)
Setup time, external FSX before CLKX
CLKX ext
[tc(H) 8]*
[tc(SCK)/2] 10*
ns
65
tsu(FSX-C)
Setup time, external FSX before CLKX
CLKX int
[tc(H) 21]*
tc(SCK)/2*
ns
66
td(CH-DX)V
Delay time, CLKX to first DX bit, FSX
CLKX ext
24*
ns
66
td(CH-DX)V
Delay time, CLKX to first DX bit, FSX
precedes CLKX high
CLKX int
14*
ns
67
td(FSX-DX)V
Delay time, FSX to first DX bit, CLKX precedes FSX
24*
ns
68
td(CH-DXZ)
Delay time, CLKX high to DX high impedance following last
data bit
14*
ns
* This parameter is not production tested.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
5962-9205804MXA 制造商:Texas Instruments 功能描述:5962-9205804MXA, 3RD GEN DSP, 50MHZ - Rail/Tube
5962-9205804MXC 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC DIGITAL SIGNAL PROCESSOR RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
5962-9205804MYA 制造商:Texas Instruments 功能描述:5962-9205804MYA, 3RD GEN DSP, 50 MHZ - Rail/Tube
5962-9205805QXA 制造商:Texas Instruments 功能描述:DSP FLOATING PT 32BIT 60MHZ 30MIPS 141CPGA - Rail/Tube
5962-9205805QYA 制造商:Texas Instruments 功能描述:DSP FLOATING PT 32BIT 60MHZ 30MIPS 132CFPAK - Rail/Tube
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