參數(shù)資料
型號(hào)： 5962-9205803MYA
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： 32-BIT, 40 MHz, OTHER DSP, CQFP132
封裝： NON CONDUCTIVE TIE BAR, CERAMIC, QFP-132
文件頁(yè)數(shù)： 33/54頁(yè)
文件大?。?/td> 1033K
代理商： 5962-9205803MYA
SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026G APRIL 1998 REVISED SEPTEMBER 2006
39
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
HOLD timing
HOLD is an asynchronous input that can be asserted at any time during a clock cycle. If the specified timings
are met, the exact sequence shown in Figure 27 occurs; otherwise, an additional delay of one clock cycle is
possible.
The NOHOLD bit of the primary-bus control register overrides the HOLD signal. When this bit is set, the device
comes out of hold and prevents future hold cycles.
Asserting HOLD prevents the processor from accessing the primary bus. Program execution continues until a
read from or a write to the primary bus is requested. In certain circumstances, the first write is pending, thus
allowing the processor to continue until a second write is encountered.
timing for HOLD/HOLDA (see Figure 28)
NO.
’C31-40
’LC31-40
’C31-50
’C31-60
UNIT
NO.
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
69
tsu(HOLD-H1L)
Setup time, HOLD before
H1 low
13
10
8
ns
70
tv(H1L-HOLDA)
Valid time, HOLDA after H1
low
0
9
0*
9
0*
7
0*
6
ns
71
tw(HOLD)
Pulse duration, HOLD low
2tc(H)
ns
72
tw(HOLDA)
Pulse duration, HOLDA low
tcH5*
ns
73
td(H1L-SH)H
Delay time, H1 low to STRB
high for a HOLD
0*
9
0*
9
0*
7
0*
6
ns
74
tdis(H1L-S)
Disable time, H1 low to
STRB to the
high-impedance state
0*
9*
0*
9*
0*
7*
0*
7*
ns
75
ten(H1L-S)
Enable time, H1 low to
STRB enabled (active)
0*
9
0*
9
0*
7
0*
6
ns
76
tdis(H1L-RW)
Disable time, H1 low to R/W
to the high-impedance state
0*
9*
0*
9*
0*
8*
0*
7*
ns
77
ten(H1L-RW)
Enable time, H1 low to R/W
enabled (active)
0*
9
0*
9
0*
7
0*
6
ns
78
tdis(H1L-A)
Disable time, H1 low to
address to the
high-impedance state
0*
9*
0*
10*
0*
8*
0*
7*
ns
79
ten(H1L-A)
Enable time, H1 low to
address enabled (valid)
0*
13
0*
13
0*
10
0*
11?
ns
80
tdis(H1H-D)
Disable time, H1 high to
data to the high-impedance
state
0*
12*
0*
9*
0*
10*
0*
7*
ns
HOLD is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exact sequence shown
in Figure 28 occurs; otherwise, an additional delay of one clock cycle is possible.
* This parameter is not production tested.
相關(guān)PDF資料
PDF描述
5962-9205805QXA 32-BIT, 60 MHz, OTHER DSP, CPGA141
5962-9309101HYA EEPROM 5V MODULE, CDIP32
5962-9315302MXX 4K X 9 MULTI-PORT SRAM, 25 ns, CQCC
596287663012X ACT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, CQCC20
5962D0053605QYX 512K X 8 STANDARD SRAM, 20 ns, CDFP36
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
5962-9205804MXA 制造商:Texas Instruments 功能描述:5962-9205804MXA, 3RD GEN DSP, 50MHZ - Rail/Tube
5962-9205804MXC 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC DIGITAL SIGNAL PROCESSOR RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
5962-9205804MYA 制造商:Texas Instruments 功能描述:5962-9205804MYA, 3RD GEN DSP, 50 MHZ - Rail/Tube
5962-9205805QXA 制造商:Texas Instruments 功能描述:DSP FLOATING PT 32BIT 60MHZ 30MIPS 141CPGA - Rail/Tube
5962-9205805QYA 制造商:Texas Instruments 功能描述:DSP FLOATING PT 32BIT 60MHZ 30MIPS 132CFPAK - Rail/Tube
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*