參數(shù)資料
型號： 5962-0721401VZC
元件分類： ADC
英文描述： 2-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP128
封裝： CERAMIC, MS-026VFB, QFP-128
文件頁數(shù)： 29/48頁
文件大小： 1421K
代理商： 5962-0721401VZC
I-Channel Offset
Addr: 2h (0010b)
Write only (0x007F)
D15
D14
D13
D12
D11
D10
D9
D8
(MSB)
Offset Value
(LSB)
D7
D6
D5
D4
D3
D2
D1
D0
Sign
1
Bits 15:8
Offset Value. The input offset of the I-Channel
ADC is adjusted linearly and monotonically by
the value in this field. 00h provides a nominal
zero offset, while FFh provides a nominal 45
mV of offset. Thus, each code step provides
0.176 mV of offset.
Default State: 0000 0000 b
Bit 7
Sign bit. 0b gives positive offset, 1b gives
negative offset.
Default State: 0b
Bit 6:0
Must be set to 1b
I-Channel Full-Scale Voltage Adjust
Addr: 3h (0011b)
Write only (0x807F)
D15
D14
D13
D12
D11
D10
D9
D8
(MSB)
Adjust Value
D7
D6
D5
D4
D3
D2
D1
D0
(LSB)
1
Bit 15:7
Full Scale Voltage Adjust Value. The input full-
scale voltage or gain of the I-Channel ADC is
adjusted linearly and monotonically with a 9 bit
data value. The adjustment range is ±20% of
the nominal 700 mV
P-P differential value.
0000 0000 0
560mV
P-P
1000 0000 0
Default Value
700mV
P-P
1111 1111 1
840mV
P-P
For best performance, it is recommended that
the value in this field be limited to the range of
0110 0000 0b to 1110 0000 0b. i.e., limit the
amount of adjustment to ±15%. The remaining
±5% headroom allows for the ADC's own full
scale variation. A gain adjustment does not
require ADC re-calibration.
Default State: 1000 0000 0b (no adjustment)
Bits 6:0
Must be set to 1b
Extended Configuration Register
Addr: 9h (1001b)
Write only (0x03FF)
D15
D14
D13
D12
D11
D10
D9
D8
TPO
RTD
DEN
IS
0
DLF
1
D7
D6
D5
D4
D3
D2
D1
D0
1
Bit 15
TPO: Test Pattern Output. When this bit is set
1b, the ADC is disengaged and a test pattern
generator is connected to the outputs
including OR. This test pattern will work with
the device in the SDR, DDR and the Non-
Demultiplex output modes.
Default State: 0b
Bit 14
RTD: Resistor Trim Disable. When this bit is
set to 1b, the input termination resistor is not
trimmed during the calibration cycle and the
DCLK output remains enabled. Note that the
ADC is calibrated regardless of this setting.
Default State: 0b
Bit 13
DES: DES Enable. Setting this bit to 1b
enables the Dual Edge Sampling Mode. In
this mode the ADCs in this device are used
to sample and convert the same analog input
in a time-interleaved manner, accomplishing
a sample rate of twice the input clock rate.
When this bit is set to 0b, the device operates
in the Non-DES Mode.
Default State: 0b
Bit 12
IS: Input Select. When this bit is set to 0b the
I- Channel input is operated upon by both
ADCs. When this bit is set to 1b the Q-
Channel input is operated on by both ADCs.
Default State: 0b
Bit 11
Must be set to 0b
Bit 10
DLF: DES Low Frequency. When this bit is
device is improved when the input clock is
less than 900 MHz.
Default State: 0b
Bits 9:0
Must be set to 1b
Q- Channel Offset
Addr: Ah (1010b)
Write only (0x007F)
D15
D14
D13
D12
D11
D10
D9
D8
(MSB)
Offset Value
(LSB)
D7
D6
D5
D4
D3
D2
D1
D0
Sign
1
Bit 15:8
Offset Value. The input offset of the Q-
Channel ADC is adjusted linearly and
monotonically by the value in this field. 00h
provides a nominal zero offset, while FFh
provides a nominal 45 mV of offset. Thus,
each code step provides about 0.176 mV of
offset.
Default State: 0000 0000 b
Bit 7
Sign bit. 0b gives positive offset, 1b gives
negative offset.
Default State: 0b
Bit 6:0
Must be set to 1b
35
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ADC08D1520QML
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