參數(shù)資料
型號(hào)： 5962-0721401VZC
元件分類： ADC
英文描述： 2-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP128
封裝： CERAMIC, MS-026VFB, QFP-128
文件頁(yè)數(shù)： 25/48頁(yè)
文件大?。?/td> 1421K
代理商： 5962-0721401VZC
sible modes: (1) Non-Demux Mode, (2) Non-Demux DES
Mode, (3) 1:2 Demux Non-DES Mode, and (4) 1:4 Demux
DES Mode. The following is a brief explanation of the terms
and modes:
1.
Non-Demux Mode: This mode is when the chip is in Non-
Demux Mode and Non-DES Mode, but it is shortened to
simply "Non-Demux Mode." The I- and Q- channels
function independently of one another. The digital output
data is available for the I- channel on DI, and for the Q-
channel on DQ.
2.
Non-Demux DES Mode: This mode is when the chip is
in Non-Demux Mode and DES Mode. The I- and Q-
channels are interleaved and function together as one
channel. The digital output data is available on the DI and
DQ busses because although the chip is in Non-Demux
Mode, both I- and Q- channels are functioning and
passing data.
3.
1:2 Demux Non-DES Mode: This mode is when the chip
is in Demux Mode and Non-DES Mode. The I- and Q-
channels function independently of one another. The
digital output data is available for the I- channel on DI and
DId, and for the Q- channel on DQ and DQd. This is
because each channel (I- channel and Q- channel) is
providing digital data in a demultiplexed manner.
4.
1:4 Demux DES Mode: This mode is when the chip is in
Demux Mode and DES Mode. The I- and Q- channels
are interleaved and function together as one channel.
The digital output data is available on the DI, DId, DQ and
DQd busses because although the chip is in Demux
Mode, both I- and Q- channels are functioning and
passing data. To avoid confusion, this mode is labeled
1:4 because the analog input signal is provided on one
channel and the digital output data is provided on four
busses.
The choice of Dual Data Rate (DDR) and Single Data Rate
(SDR) will only affect the speed of the output Data Clock
(DCLK). Once the DES Modes and Demux Modes have been
chosen, the data output rate is also fixed. In the case of SDR,
the DCLK runs at the same rate as the output data; output
data may transition with either the rising or falling edge of
DCLK. In the case of DDR, the DCLK runs at half the rate of
the output data; the output data transitions on both rising and
falling edges of the DCLK.
1.1.6 The LVDS Outputs
The data outputs, the Out Of Range (OR) and DCLK, are
LVDS. Output current sources provide 3 mA of output current
to a differential 100 Ohm load when the OutV input (pin 14) is
high or 2.2 mA when the OutV input is low. For short LVDS
lines and low noise systems, satisfactory performance may
be realized with the OutV input low, which results in lower
power consumption. If the LVDS lines are long and/or the
system in which the ADC08D1520 is used is noisy, it may be
necessary to tie the OutV pin high.
The LVDS data output have a typical common mode voltage
of 800 mV when the V
BG pin is left floating. This common
mode voltage can be increased to 1.1V by tying the V
BG pin
to V
A if a higher common mode is required.
IMPORTANT NOTE:
Tying the V
BG pin to VA will also in-
crease the differential LVDS output voltage by up to 40mV.
1.1.7 Power Down
The ADC08D1520 is in the active state when the Power Down
pin (PD) is low. When the PD pin is high, the device is in the
Power Down Mode. In this Power Down Mode the data output
pins (positive and negative) are put into a high impedance
state and the devices power consumption is reduced to a
minimal level. The DCLK+/- and OR +/- are not tri-stated, they
are weakly pulled down to ground internally. Therefore when
both I- Channel and Q- Channel are powered down the DCLK
+/- and OR +/- should not be terminated to a DC voltage.
A high on the PDQ pin will power down the Q- Channel and
leave the I- channel active. There is no provision to power
down the I- Channel independently of the Q- Channel. Upon
return to normal operation, the pipeline will contain meaning-
less information.
If the PD input is brought high while a calibration is running,
the device will not go into power down until the calibration
sequence is complete. However, if power is applied and PD
is simultaneously ramped, the device will not calibrate until
the PD input goes low. If a calibration is requested while the
device is powered down, the calibration request will be com-
pletely ignored. Calibration will function with the Q- Channel
powered down, but that channel will not be calibrated if PDQ
is high. If the Q- Channel is subsequently to be used, it is
necessary to perform a calibration after PDQ is brought low.
1.2 NON-EXTENDED CONTROL/EXTENDED CONTROL
The ADC08D1520 may be operated in one of two modes. In
the simpler Non-Extended Control Mode, the user affects
available configuration and control of the device through sev-
eral control pins. The "Extended Control Mode" provides ad-
ditional configuration and control options through a serial
interface and a set of 9 registers. Extended Control Mode is
selected by setting pin 41 to logic low. The choice of control
modes is required to be a fixed selection and is not intended
to be switched dynamically while the device is operational.
Table 3 shows how several of the device features are affected
by the control mode chosen.
31
www.national.com
ADC08D1520QML
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