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| 型號(hào)： | 5962-0721401VZC |
| 元件分類： | ADC |
| 英文描述： | 2-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP128 |
| 封裝： | CERAMIC, MS-026VFB, QFP-128 |
| 文件頁數(shù)： | 24/48頁 |
| 文件大?。?/td> | 1421K |
| 代理商： | 5962-0721401VZC |
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TABLE 1. Input Channel Samples Produced at Data Outputs in 1:2 Demultiplexed Mode**
Data Outputs
(Always sourced with
respect to fall of DCLK+)
Non DES Sampling Mode
Dual-Edge Sampling Mode (DES)
I- Channel Selected
Q- Channel Selected *
DI
I- Channel Input Sampled with
Fall of CLK 13 cycles earlier.
I- Channel Input Sampled
with Fall of CLK 13 cycles
earlier.
Q- Channel Input Sampled with
Fall of CLK 13 cycles earlier.
DId
I- Channel Input Sampled with
Fall of CLK 14 cycles earlier.
I- Channel Input Sampled
with Fall of CLK 14 cycles
earlier.
Q- Channel Input Sampled with
Fall of CLK 14 cycles earlier.
DQ
Q- Channel Input Sampled with
Fall of CLK 13 cycles earlier.
I- Channel Input Sampled
with Rise of CLK 13.5 cycles
earlier.
Q- Channel Input Sampled with
Rise of CLK 13.5 cycles earlier.
DQd
Q- Channel Input Sampled with
Fall of CLK 14 cycles earlier.
I- Channel Input Sampled
with Rise of CLK 14.5 cycles
earlier.
Q- Channel Input Sampled with
Rise of CLK 14.5 cycles earlier.
* Note that, in DES + Non-DES Mode, only the I- Channel is sampled. In DES + Extended Control Mode, I- Channel or Q-
Channel can be sampled.
** Note that, in the Non-Demultiplexed Mode, the DId and DQd outputs are disabled and are high impedance.
TABLE 2. Input Channel Samples Produced at Data Outputs in 1:1 Demultiplexed Mode
Data Outputs
(Sourced with respect to fall of DCLK+)
Non-DES Mode
DES Mode
DI
I- Channel Input Sampled with Fall of CLK
13 cycles earlier.
I- Channel Input Sampled with Fall of CLK
13 cycles earlier.
Dld
No output.
DQ
Q- Channel Input Sampled with Fall of
CLK 13 cycles earlier.
Q- Channel Input Sampled with Fall of
CLK 13.5 cycles earlier.
DQd
No output.
1.1.5.2 OutEdge and Demultiplex Control Setting
To help ease data capture in the SDR Mode, the output data
may be caused to transition on either the positive or the neg-
ative edge of the output data clock (DCLK). In the Non-
Extended Control Mode, this is chosen with the OutEdge input
(pin 4). A high on the OutEdge input pin causes the output
data to transition on the rising edge of DCLK+, while ground-
ing this input causes the output to transition on the falling edge
of DCLK. See 2.5.3 Output Edge Synchronization. When in
the Extended Control Mode, the OutEdge is selected using
the OED bit in the Configuration Register. This bit has two
functions. In the single data rate (SDR) Mode, the bit functions
as OutEdge and selects the DCLK edge with which the data
transitions. In the Double Data Rate (DDR) Mode, this bit se-
lects whether the device is in Non-Demultiplex or 1:2 Demul-
tiplex Mode. In the DDR case, the DCLK has a 0° phase
relationship with the output data independent of the demulti-
plexer selection.
For 1:2 Demux DDR 0 deg Mode, there are five, as opposed
to four cycles of CLK delay from the deassertion of
DCLK_RST to the Synchronizing Edge. See 1.5 MULTIPLE
1.1.5.3 Double Data Rate
A choice of single data rate (SDR) or double data rate (DDR)
output is offered. With single data rate the output clock
(DCLK) frequency is the same as the data rate of the two out-
put buses. With double data rate the DCLK frequency is half
the data rate and data is sent to the outputs on both edges of
DCLK. DDR clocking is enabled in Non-Extended Control
Mode by tying pin 4 to V
A/2.
1.1.5.4 Clocking Summary
The chip may be in one of four modes, depending on the Dual-
Edge Sampling (DES) selection and the demultiplex selec-
tion. For the DES selection, there are two possibilities: Non-
DES Mode and DES Mode. In Non-DES Mode, each of the
channels (I-channel and Q-channel) functions independently,
i.e. the chip is a dual 1.5 GSPS A/D converter. In DES Mode,
the I- and Q-channels are interleaved and function together
as one 3.0 GSPS A/D converter. For the demultiplex selec-
tion, there are also two possibilities: Demux Mode and Non-
Demux Mode. The I-channel has two 8-bit output busses
associated with it: DI and DId. The Q-channel also has two 8-
bit output busses associated with it: DQ and DQd. In Demux
Mode, the channel is demultiplexed by 1:2. In Non-Demux
Mode, the channel is not demultiplexed. Note that Non-De-
mux Mode is also sometimes referred to as 1:1 Demux Mode.
For example, if the I-channel was in Non-Demux Mode, the
corresponding digital output data would be available on only
the DI bus. If the I-channel was in Demux Mode, the corre-
sponding digital output data would be available on both the
DI and DId busses, but at half the rate of Non-Demux Mode.
Given that there are two DES Mode selections (DES Mode
and Non-DES Mode) and two demultiplex selections (Demux
Mode and Non-Demux Mode), this yields a total of four pos-
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ADC08D1520QML
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