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參數(shù)資料
| 型號(hào)： | 5962-0721401VZC |
| 元件分類： | ADC |
| 英文描述： | 2-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP128 |
| 封裝： | CERAMIC, MS-026VFB, QFP-128 |
| 文件頁數(shù)： | 26/48頁 |
| 文件大小： | 1421K |
| 代理商： | 5962-0721401VZC |
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TABLE 3. Features and Modes
Feature
Non-Extended Control Mode
Extended Control Mode
SDR or DDR Clocking Selected with pin 4
Selected with bit 10 nDE in the Configuration Register
(Addr-1h; bit-10)
DDR Clock Phase
Not Selectable (0° Phase Only)
Selected with DCP in the Configuration
Register (Addr-1h; bit-11)
SDR Data transitions
with rising or falling
DCLK edge
SDR Data transitions with rising
edge of DCLK+ when pin 4 is high
and on falling edge when low.
Selected with OED in the Configuration Register (Addr-1h; bit-8)
LVDS output level
Normal differential data and DCLK
amplitude selected when pin 3 is
high and reduced amplitude
selected when low.
Selected with OV in the Configuration Register (Addr-1h; bit-9)
Full-Scale Range
Normal input full-scale range
selected when pin 14 is high and
reduced range when low.
Selected range applies to both
channels.
Up to 512 step adjustments over a nominal range specified in 1.4
REGISTER DESCRIPTION. Separate range selected for I-
Channel and Q- Channels. Selected using Full Range
Registers (Addr-3h and Bh; bit-7 thru 15)
Input Offset Adjust
Not possible
512 steps of adjustment using the input Offset register specified
in 1.4 REGISTER DESCRIPTION for each channel using Input
Offset registers (Addr-2h and Ah; bit-7 thru 15)
Dual Edge Sampling
Selection
Enabled with pin 127 set to V
A/2
Enabled by programming DEN in the Extended Configuration
Register (Addr-9h; bit-13 )
Dual Edge Sampling
Input Channel
Selection
Only I-Channel Input can be used
Either I- Channel or Q- Channel input may be sampled by both
ADCs.
Test Pattern
Not possible
A test pattern can be made present at the data outputs by setting
TPO to 1b in Extented Configuration Register (Addr-9h; bit-15)
Resistor Trim Disable Not possible
The DCLK outputs will continuously be present when RTD is set
to 1b in Extented Configuration Register (Addr-9h; bit-14)
Selectable Output
Demultiplexer
Not possible
If the device is set in DDR, the output can be programmed to be
non-demultiplex. When OED in Configuration Register is set 1b
(Addr-1h; 8-bit), this selects non-demultiplex. If OED is set 0b,
this selects 1:2 demultiplex.
Second DCLK Output Not possible
The OR outputs can be programmed to become a second DCLK
output when nSD is set 0b in Configuration Register
(Addr-1h; bit-13).
Sampling Clock Phase
Adjust
Not possible
The sampling clock phase can be manually adjusted through the
Coarse and Intermediate Register (Addr-Fh; bit-14 to 7) and Fine
register (Addr-Dh; bit-15 to 8)
IMPORTANT NOTE:
When the device is powered up in the
Extended Control Mode, the Registers are loaded with invalid
data and the Registers come up in an unknown state. Before
initiating a calibration the registers must be written to and
programmed into a known state. If the device is powered up
in the Non-Extended Control Mode and the user switches to
the Extended Control Mode after the part has stabilized, the
registers will load with the register default states described in
Table 4.
www.national.com
32
ADC08D1520QML
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