參數(shù)資料
型號(hào)： 5962-0520601VZX
元件分類(lèi)： ADC
英文描述： PROPRIETARY METHOD ADC, CQFP128
封裝： CERAMIC, QFP-128
文件頁(yè)數(shù)： 3/42頁(yè)
文件大?。?/td> 1310K
代理商： 5962-0520601VZX
AC Parameters
The following specifications apply after calibration for V
A = VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential
870mV
P-P, CL = 10 pF, Differential, a.c. coupled Sinewave Input Clock, fCLK = 1 GHz at 0.5VP-P with 50% duty cycle, VBG = Floating,
Non-Extended Control Mode, SDR Mode, R
EXT = 3300 ±0.1%, Analog Signal Source Impedance = 100Ω Differential. Boldface
limits apply for T
A = TMIN to TMAX (Notes 5, 6)
Symbol
Parameters
Conditions
Notes
Typical
(Note 7)
Min
Max
Units
Sub -
groups
NORMAL MODE (Non DES) DYNAMIC CONVERTER CHARACTERISTICS
ENOB
Effective Number of Bits
f
IN = 100 MHz, VIN = FSR 0.5 dB
7.5
Bits
f
IN = 248 MHz, VIN = FSR 0.5 dB
7.4
7.0
Bits
4, 5, 6
f
IN = 498 MHz, VIN = FSR 0.5 dB
7.4
7.0
Bits
4, 5, 6
SINAD
Signal-to-Noise Plus
Distortion Ratio
f
IN = 100 MHz, VIN = FSR 0.5 dB
47
dB
f
IN = 248 MHz, VIN = FSR 0.5 dB
46.3
43.9
dB
4, 5, 6
f
IN = 498 MHz, VIN = FSR 0.5 dB
46.3
43.9
dB
4, 5, 6
SNR
Signal-to-Noise Ratio
f
IN = 100 MHz, VIN = FSR 0.5 dB
48
dB
f
IN = 248 MHz, VIN = FSR 0.5 dB
47.1
44
dB
4, 5, 6
f
IN = 498 MHz, VIN = FSR 0.5 dB
47.1
44
dB
4, 5, 6
THD
Total Harmonic Distortion
f
IN = 100 MHz, VIN = FSR 0.5 dB
-55
dB
f
IN = 248 MHz, VIN = FSR 0.5 dB
-55
47.5
dB
4, 5, 6
f
IN = 498 MHz, VIN = FSR 0.5 dB
-55
47.5
dB
4, 5, 6
SFDR
Spurious Free Dynamic
Range
f
IN = 248 MHz, VIN = FSR 0.5 dB
57
dB
f
IN = 498 MHz, VIN = FSR 0.5 dB
57
47
dB
4, 5, 6
f
CLK1
Maximum Input Clock
Frequency
Normal Mode (non DES)
1.2
1.0
GHz
4, 5, 6
INTERLEAVE MODE (DES Pin 127=Float) - DYNAMIC CONVERTER CHARACTERISTICS
ENOB
Effective Number of Bits
f
IN = 248 MHz, VIN = FSR 0.5 dB
7.3
Bits
f
IN = 498 MHz, VIN = FSR 0.5 dB
7.3
6.8
Bits
4, 5, 6
SINAD
Signal to Noise Plus Distortion
Ratio
f
IN = 248 MHz, VIN = FSR 0.5 dB
46
dB
f
IN = 498 MHz, VIN = FSR 0.5 dB
46
42.5
dB
4, 5, 6
SNR
Signal to Noise Ratio
f
IN = 248 MHz, VIN = FSR 0.5 dB
46.4
dB
f
IN = 498 MHz, VIN = FSR 0.5 dB
46.4
43
dB
4, 5, 6
THD
Total Harmonic Distortion
f
IN = 248 MHz, VIN = FSR 0.5 dB
-58
dB
f
IN = 498 MHz, VIN = FSR 0.5 dB
-58
49
dB
4, 5, 6
SFDR
Spurious Free Dynamic
Range
f
IN = 248 MHz, VIN = FSR 0.5 dB
57
dB
f
IN = 498 MHz, VIN = FSR 0.5 dB
57
47
dB
4, 5, 6
AC Timing Parameters
The following specifications apply after calibration for V
A = VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential
870mV
P-P, CL = 10 pF, Differential, a.c. coupled Sinewave Input Clock, fCLK = 1 GHz at 0.5VP-P with 50% duty cycle, VBG = Floating,
Non-Extended Control Mode, SDR Mode, R
EXT = 3300 ±0.1%, Analog Signal Source Impedance = 100Ω Differential. Boldface
limits apply for T
A = TMIN to TMAX (Notes 5, 6)
Symbol
Parameters
Conditions
Notes
Typical
(Note 7)
Min
Max
Units
Sub -
groups
AC TIMING PARAMETERS
t
RPW
Reset Pulse Width
4
Clock
Cycles
9, 10, 11
Serial Clock Low Time
4
ns
9, 10, 11
Serial Clock High Time
4
ns
9, 10, 11
t
CAL_L
CAL Pin Low Time
640
Clock
Cycles
9, 10, 11
t
CAL_H
CAL Pin High Time
640
Clock
Cycles
9, 10, 11
11
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ADC08D1000QML
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