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| 型號(hào)： | 5962-0520601VZX |
| 元件分類： | ADC |
| 英文描述： | PROPRIETARY METHOD ADC, CQFP128 |
| 封裝： | CERAMIC, QFP-128 |
| 文件頁數(shù)： | 27/42頁 |
| 文件大小： | 1310K |
| 代理商： | 5962-0520601VZX |
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settings or initiated a calibration cycle (during the calibration
cycle the ADC cannot be used). In the QML version of the
ADC08D1000, all internal registers resets will be connected
to the calibration reset, not POR. Therefore, a POR during
normal operations will not cause registers to be erased and,
if the CAL pin is kept at a logic high, POR initiated calibration
will not occur. In the QML version of the ADC08D1000, the
POR will only be used to reset the self-timer for AUTO-CAL,
whose functionality is maintained for backwards compatibility
only. Also, when using the QML version of the ADC08D1000
as described in this paragraph, the calibration registers will
initiate randomly and remain so until a calibration cycle has
been initiated. In the QML version of the ADC08D1000, with
the CAL pin kept at a logic high, a POR event essentially does
“nothing” except reset the AUTO-CAL self-timer.
2.2 THE REFERENCE VOLTAGE
The voltage reference for the ADC08D1000 is derived from a
1.254V bandgap reference, a buffered version of which is
made available at pin 31, V
BG for user convenience and has
an output current capability of ±100
μA. This reference volt-
age should be buffered if more current is required.
The internal bandgap-derived reference voltage has a nomi-
nal value of 650 mV or 870 mV, as determined by the FSR
pin and described in Section 1.1.4.
There is no provision for the use of an external reference volt-
age, but the full-scale input voltage can be adjusted through
a Configuration Register in the Extended Control mode, as
explained in Section 1.2.
Differential input signals up to the chosen full-scale level will
be digitized to 8 bits. Signal excursions beyond the full-scale
range will be clipped at the output. These large signal excur-
sions will also activate the OR output for the time that the
signal is out of range. See Section 2.3.2.
One extra feature of the V
BG pin is that it can be used to raise
the common mode voltage level of the LVDS outputs. The
output offset voltage (V
OS) is typically 800mV when the VBG
pin is used as an output or left unconnected. To raise the
LVDS offset voltage to a typical value of 1200mV the V
BG pin
can be connected directly to the supply rails.
2.3 THE ANALOG INPUT
The analog input is a differential one to which the signal
source may be a.c. coupled or d.c. coupled. The full-scale
input range is selected with the FSR pin to be 650 mV
P-P or
870 mV
P-P, or can be adjusted to values between 560 mVP-
P and 840 mVP-P in the Extended Control mode through the
Serial Interface. For best performance, it is recommended
that the full-scale range be kept between 595 mV
P-P and 805
mV
P-P in the Extended Control mode.
Table 5 gives the input to output relationship with the FSR pin
high and the normal (non-extended) mode is used. With the
FSR pin grounded, the millivolt values in Table 5 are reduced
to 75% of the values indicated. In the Enhanced Control
Mode, these values will be determined by the full scale range
and offset settings in the Control Registers.
TABLE 5. DIFFERENTIAL INPUT TO OUTPUT
RELATIONSHIP (Non-Extended Control Mode, FSR High)
V
IN+
V
IN
Output Code
V
CM 217.5mV
V
CM + 217.5mV
0000 0000
V
CM 109 mV
V
CM + 109 mV
0100 0000
V
CM
V
CM
0111 1111 /
1000 0000
V
CM + 109 mV
V
CM 109 mV
1100 0000
V
CM + 217.5mV
V
CM 217.5mV
1111 1111
The buffered analog inputs simplify the task of driving these
inputs and the RC pole that is generally used at sampling ADC
inputs is not required. If it is desired to use an amplifier circuit
before the ADC, use care in choosing an amplifier with ade-
quate noise and distortion performance and adequate gain at
the frequencies used for the application.
Note that a precise d.c. common mode voltage must be
present at the ADC inputs. This common mode voltage,
V
CMO, is provided on-chip when a.c. input coupling is used
and the input signal is a.c. coupled to the ADC.
When the inputs are a.c. coupled, the V
CMO output must be
grounded, as shown in Figure 12. This causes the on-chip
V
CMO voltage to be connected to the inputs through on-chip
50k-Ohm resistors.
IMPORTANT NOTE
: An Analog input channel that is not used
(e.g. in DES Mode) should be left floating when the inputs are
a.c. coupled. Do not connect an unused analog input to
ground.
20180244
FIGURE 12. Differential Input Drive
When the d.c. coupled mode is used, a common mode volt-
age must be provided at the differential inputs. This common
mode voltage should track the V
CMO output pin. Note that the
V
CMO output potential will change with temperature. The com-
mon mode output of the driving device should track this
change.
IMPORTANT NOTE:
An analog input channel that is not used
(e.g. in DES Mode) should be tied to the V
CMO voltage when
the inputs are d.c coupled. Do not connect unused analog
inputs to ground.
Full-scale distortion performance falls off rapidly as the
input common mode voltage deviates from V
CMO. This is
a direct result of using a very low supply voltage to min-
imize power. Keep the input common voltage within 50
mV of V
CMO.
Performance is as good in the d.c. coupled mode as it is
in the a.c. coupled mode, provided the input common
mode voltage at both analog inputs remain within 50 mV
of V
CMO.
33
www.national.com
ADC08D1000QML
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