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| 型號： | 5962-0520601VZX |
| 元件分類： | ADC |
| 英文描述： | PROPRIETARY METHOD ADC, CQFP128 |
| 封裝： | CERAMIC, QFP-128 |
| 文件頁數(shù)： | 26/42頁 |
| 文件大?。?/td> | 1310K |
| 代理商： | 5962-0520601VZX |
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Bit 15
DES Enable. Setting this bit to 1b enables the
Dual Edge Sampling mode. In this mode the
ADCs in this device are used to sample and
convert the same analog input in a time-
interleaved manner, accomplishing a
sampling rate of twice the input clock rate.
When this bit is set to 0b, the device operates
in the normal dual channel mode.
POR State: 0b
Bit 14
Automatic Clock Phase Control. (ACP) Setting
this bit to 1b enables the Automatic Clock
Phase Control. In this mode the DES Coarse
and Fine manual controls are disabled. A
phase detection circuit continually adjusts the
I and Q sampling edges to be 180 degrees out
of phase. When this bit is set to 0b, the sample
(input) clock delay between the I and Q
channels is set manually using the DES
Coarse and Fine Adjust registers. (See
Section 2.4.5 for important application
information) Using the ACP Control option
is recommended over the manual DES
settings
.
POR State: 0b
Bits 13:0
Must be set to 1b
1.4.1 Note Regarding Extended Mode Offset Correction
When using the I or Q channel Offset Adjust registers, the
following information should be noted.
For offset values of +0000 0000 and -0000 0000, the actual
offset is not the same. By changing only the sign bit in this
case, an offset step in the digital output code of about 1/10th
of an LSB is experienced. This is shown more clearly in the
Figure below.
20180230
FIGURE 11. Extended Mode Offset Behaviour
1.5 MULTIPLE ADC SYNCHRONIZATION
The ADC08D1000QML has the capability to precisely reset
its sampling clock input to DCLK output relationship as de-
termined by the user-supplied DCLK_RST pulse. This allows
multiple ADCs in a system to have their DCLK (and data) out-
puts transition at the same time with respect to the shared
CLK input that they all use for sampling.
The DCLK_RST signal must observe some timing require-
Timing Diagrams. The DCLK_RST pulse must be of a mini-
mum width and its deassertion edge must observe setup and
hold times with respect to the CLK input rising edge. These
times are specified in the AC Electrical Characteristics Table.
The DCLK_RST signal can be asserted asynchronous to the
input clock. If DCLK_RST is asserted, the DCLK output is held
in a designated state. The state in which DCLK is held during
the reset period is determined by the mode of operation (SDR/
DDR) and the setting of the Output Edge configuration pin or
bit. (Refer to Figure 6, Figure 7 and Figure 8 for the DCLK
reset state conditions). Therefore, depending upon when the
DCLK_RST signal is asserted, there may be a narrow pulse
on the DCLK line during this reset event. When the
DCLK_RST signal is de-asserted in synchronization with the
CLK rising edge, the next CLK falling edge synchronizes the
DCLK output with those of other ADC08D1000QMLs in the
system. The DCLK output is enabled again after a constant
delay (relative to the input clock frequency) which is equal to
the CLK input to DCLK output delay (t
SD). The device always
exhibits this delay characteristic in normal operation.
The DCLK-RST pin should NOT be brought high while the
calibration process is running (while CalRun is high). Doing
so could cause a digital glitch in the digital circuitry, resulting
in corruption and invalidation of the calibration.
2.0 Applications Information
2.1 APPLICATIONS IN RADIATION ENVIRONMENTS
Applying the ADC08D1000 in a radiation environment should
be done with careful consideration to that environment. The
QMLV version of this part has been rated to tolerate a high
total dose of ionizing radiation by test method 1019 of MIL-
STD-883, it is also designed to withstand SEE (Single Event
Effects) and greatly mitigate these effects, however, there are
still some recommendations and cautions.
Extended Control mode,
using the serial interface feature,
should not be used in radiation environments. This is because
the D Flip Flops used in the serial interface registers are not
SET/SEU immune. Also, the serial interface is a write-only
interface, and a register that has changed states cannot be
read back and, therefore, is undetectable.
Dual-Edge Sampling Mode,
DES Mode should not be used
in radiation environments. This is because the cal circuitry
when in DES Mode is not SET/SEU (Single Event Transient
and Single Event Upset, both are types of SEE effects) im-
mune.
Floating pins.
There are three tri-level pins which activate
the following modes when left floating: FSR/ECE, OutEdge/
DDR/SDATA, and CalDly/DES/SCS. As pointed out in the last
paragraph, Extended Control mode should not be used in ra-
diation environments, thus, the FSR/ECE mode should not be
left floating or connected to Va/2, either a logic high or logic
low should be applied to this pin. If DDR or DES modes need
to be used, then it is strongly recommended that the floating
method of establishing Va/2 on these pins not be employed.
Due to the potential of increased leakage of the input protec-
tion diodes after large ionizing doses, the midpoint voltage
(Va/2 or 0.95V) should be voltage forced or formed with a
resistor divider from the analog supply to ground with two 2K
ohm resistors. The internal voltage divider resistors provide
too little current to set the midpoint voltage reliably in radiation
environments.
The CAL pin
should be kept at a logic high at all times during
normal operation in radiation environments and calibration
should be manually initiated by bringing the CAL pin low and
then back high again. This will prevent POR initiated calibra-
tions. The POR circuit is susceptible to SET. A POR during
normal operation would not be acceptable if it erased register
www.national.com
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ADC08D1000QML
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