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| 型號： | 5962-0520601VZX |
| 元件分類： | ADC |
| 英文描述： | PROPRIETARY METHOD ADC, CQFP128 |
| 封裝： | CERAMIC, QFP-128 |
| 文件頁數(shù)： | 28/42頁 |
| 文件大?。?/td> | 1310K |
| 代理商： | 5962-0520601VZX |
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If d.c. coupling is used, it is best to servo the input common
mode voltage, using the V
CMO pin, to maintain optimum per-
formance. An example of this type of circuit is shown in Figure
20180255
FIGURE 13. Example of Servoing the Analog Input with
V
CMO
One such circuit should be used in front of the V
IN+ input and
another in front of the V
IN input. In that figure, RD1, RD2 and
R
D3 are used to divide the VCMO potential so that, after being
gained up by the amplifier, the input common mode voltage
is equal to V
CMO from the ADC. RD1 and RD2 are split to allow
the bypass capacitor to isolate the input signal from V
CMO.
R
IN, RD2 and RD3 will divide the input signal, if necessary. Ca-
pacitor "C" in Figure 13 should be chosen to keep any com-
ponent of the input signal from affecting V
CMO.
Be sure that the current drawn from the V
CMO output does not
exceed 100
μA.
The Input impedance in the d.c. coupled mode (V
CMO pin not
grounded) consists of a precision 100
resistor between V
IN
+ and V
IN and a capacitance from each of these inputs to
ground. In the a.c. coupled mode the input appears the same
except there is also a resistor of 50K between each analog
input pin and the V
CMO potential.
Driving the inputs beyond full scale will result in a saturation
or clipping of the reconstructed output.
2.3.1 Handling Single-Ended Input Signals
There is no provision for the ADC08D1000 to adequately pro-
cess single-ended input signals. The best way to handle
single-ended signals is to convert them to differential signals
before presenting them to the ADC. The easiest way to ac-
complish single-ended to differential signal conversion is with
an appropriate balun-connected transformer, as shown in
20180211
FIGURE 14. Single-Ended To Differential Signal
Conversion With A Balun-Connected Transformer
The 100 Ohm external resistor placed accross the output ter-
minals of the balun in parallel with the ADC08D1000's on-chip
100 Ohm resistor makes a 50 Ohms differential impedance
at the balun output. Or, 25 Ohms to virtual ground at each of
the balun output terminals.
Looking into the balun, the source sees the impedance of the
first coil in series with the impedance at the output of that coil.
Since the transformer has a 1:1 turns ratio, the impedance
across the first coil is exactly the same as that at the output
of the second coil, namely 25 Ohms to virtual ground. So, the
25 Ohms across the first coil in series with the 25 Ohms at its
output gives 50 Ohms total impedance to match the source.
2.3.2 Out Of Range (OR) Indication
When the conversion result is clipped the Out of Range output
is activated such that OR+ goes high and OR- goes low. This
output is active as long as accurate data on either or both of
the buses would be outside the range of 00h to FFh.
2.3.3 Full-Scale Input Range
As with all A/D Converters, the input range is determined by
the value of the ADC's reference voltage. The reference volt-
age of the ADC08D1000 is derived from an internal band-gap
reference. The FSR pin controls the effective reference volt-
age of the ADC08D1000 such that the differential full-scale
input range at the analog inputs is 870 mV
P-P with the FSR
pin high, or is 650 mV
P-P with FSR pin low. Best SNR is ob-
tained with FSR high, but better distortion and SFDR are
obtained with the FSR pin low.
2.4 THE CLOCK INPUTS
The ADC08D1000 has differential LVDS clock inputs, CLK+
and CLK-, which must be driven with an a.c. coupled, differ-
ential clock signal. Although the ADC08D1000 is tested and
its performance is guaranteed with a differential 1.0 GHz
clock, it typically will function well with input clock frequencies
indicated in the Electrical Characteristics Table. The clock in-
puts are internally terminated and biased. The input clock
signal must be capacitively coupled to the clock pins as indi-
cated in Figure 15.
Operation up to the sample rates indicated in the Electrical
Characteristics Table is typically possible if the maximum am-
bient temperatures indicated are not exceeded. Operating at
higher sample rates than indicated for the given ambient tem-
perature may result in reduced device reliability and product
lifetime. This is because of the higher power consumption and
die temperatures at high sample rates. Important also for re-
liability is proper thermal management . See Section 2.7.2.
20180247
FIGURE 15. Differential (LVDS) Input Clock Connection
The differential input clock line pair should have a character-
istic impedance of 100
and (when using a balun), be termi-
nated at the clock source in that (100
) characteristic
impedance. The input clock line should be as short and as
direct as possible. The ADC08D1000 clock input is internally
terminated with an untrimmed 100
resistor.
Insufficient input clock levels will result in poor dynamic per-
formance. Excessively high input clock levels could cause a
change in the analog input offset voltage. To avoid these
www.national.com
34
ADC08D1000QML
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