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參數(shù)資料
| 型號： | 5962-0423101QXA |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT RESISTANCE LADDER ADC, PARALLEL ACCESS, CDFP24 |
| 封裝： | CERPACK, DFP-24 |
| 文件頁數(shù)： | 5/17頁 |
| 文件大?。?/td> | 676K |
| 代理商： | 5962-0423101QXA |
Applications Information (Continued)
3.0 POWER SUPPLY CONSIDERATIONS
A/D converters draw sufficient transient current to corrupt
their own power supplies if not adequately bypassed. A
10 F tantalum or aluminum electrolytic capacitor should be
placed within an inch (2.5 cm) of the A/D power pins, with a
0.1 F ceramic chip capacitor placed within one centimeter
of the converter’s power supply pins. Leadless chip capaci-
tors are preferred because they have low lead inductance.
While a single voltage source is recommended for the V
A
and V
DR
supplies of the ADC08200, these supply pins
should be well isolated from each other to prevent any digital
noise from being coupled into the analog portions of the
ADC. A choke or 27
resistor is recommended between
these supply lines with adequate bypass capacitors close to
the supply pins.
As is the case with all high speed converters, the ADC08200
should be assumed to have little power supply rejection.
None of the supplies for the converter should be the supply
that is used for other digital circuitry in any system with a lot
of digital power being consumed. The ADC supplies should
be the same supply used for other analog circuitry.
No pin should ever have a voltage on it that is in excess of
the supply voltage or below ground by more than 300 mV,
not even on a transient basis. This can be a problem upon
application of power and power shut-down. Be sure that the
supplies to circuits driving any of the input pins, analog or
digital, do not come up any faster than does the voltage at
the ADC08200 power pins.
4.0 THE DIGITAL INPUT PINS
The ADC08200 has two digital input pins: The PD pin and
the Clock pin.
4.1 The PD Pin
The Power Down (PD) pin, when high, puts the ADC08200
into a low power mode where power consumption is reduced
to about 1.4 mW with the clock running, or to about 1 mW
with the clock held low. Output data is valid and accurate
about 1 microsecond after the PD pin is brought low.
The digital output pins retain the last conversion output code
when either the clock is stopped or the PD pin is high.
4.2 The ADC08200 Clock
Although the ADC08200 is tested and its performance is
guaranteed with a 200 MHz clock, it typically will function
well with clock frequencies from 10 MHz to 230 MHz.
The low and high times of the clock signal can affect the
performance of any A/D Converter. Because achieving a
precise duty cycle is difficult, the ADC08200 is designed to
maintain performance over a range of duty cycles. While it is
specified and performance is guaranteed with a 50% clock
duty cycle and 200 Msps, ADC08200 performance is typi-
cally maintained with clock high and low times of 0.65 ns and
0.87 ns, respectively, corresponding to a clock duty cycle
range of 13% to 82.5% with a 200 MHz clock. Note that
minimum low and high times may not be simultaneously
asserted.
20149134
FIGURE 4. The input amplifier should incorporate some gain for best performance (see text).
ADC08200QML
www.national.com
13
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