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參數(shù)資料
| 型號： | 5962-0423101QXA |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT RESISTANCE LADDER ADC, PARALLEL ACCESS, CDFP24 |
| 封裝： | CERPACK, DFP-24 |
| 文件頁數(shù)： | 3/17頁 |
| 文件大?。?/td> | 676K |
| 代理商： | 5962-0423101QXA |
Functional Description
The ADC08200 uses a new, unique architecture that
achieves over 7 effective bits at input frequencies up to and
beyond 100 MHz.
The analog input signal that is within the voltage range set by
V
RT and VRB is digitized to eight bits. Input voltages below
V
RB will cause the output word to consist of all zeroes. Input
voltages above V
RT will cause the output word to consist of
all ones.
Incorporating a switched capacitor bandgap, the ADC08200
exhibits a power consumption that is proportional to fre-
quency, limiting power consumption to what is needed at the
clock rate that is used. This and its excellent performance
over a wide range of clock frequencies makes it an ideal
choice as a single ADC for many 8-bit needs.
Data is acquired at the rising edge of the clock and the digital
equivalent of that data is available at the digital outputs 6
clock cycles plus t
OD later. The ADC08200 will convert as
long as the clock signal is present. The output coding is
straight binary.
The device is in the active state when the Power Down pin
(PD) is low. When the PD pin is high, the device is in the
power down mode, where the output pins hold the last
conversion before the PD pin went high and the device
consumes just 1.4 mW . Holding the clock input low will
further reduce the power consumption in the power down
mode to about 1 mW.
Applications Information
1.0 REFERENCE INPUTS
The reference inputs V
RT and VRB are the top and bottom of
the reference ladder, respectively. Input signals between
these two voltages will be digitized to 8 bits. External volt-
ages applied to the reference input pins should be within the
range specified in the Operating Ratings table (0.5V to (V
A
0.3V) for V
RT and 100 mV to (VRT 0.5V) for VRB). Any
device used to drive the reference pins should be able to
source sufficient current into the V
RT pin and sink sufficient
current from the V
RB pin.
The reference bias circuit of Figure 2 is very simple and the
performance is adequate for many applications. However,
circuit tolerances will lead to a wide reference voltage range.
Better reference stability can be achieved by driving the
reference pins with low impedance sources.
The circuit of Figure 3 will allow a more accurate setting of
the reference voltages. The lower amplifier must have bipo-
lar supplies as its output voltage must go negative to force
V
RB to any voltage below the VBE of the PNP transistor. Of
course, the divider resistors at the amplifier input could be
changed to suit your reference voltage needs, or the divider
can be replaced with potentiometers for precise settings.
The bottom of the ladder (V
RB) may simply be returned to
ground if the minimum input signal excursion is 0V. Be sure
that the driving source can source sufficient current into the
V
RT pin and sink enough current from the VRB pin to keep
these pins stable.
The LMC662 amplifier shown was chosen for its low offset
voltage and low cost. V
RT should always be at least 0.5V
more positive than V
RB to minimize noise.
The V
RM pin is the center of the reference ladder and should
be bypassed to a quiet point in the analog ground plane with
a 0.1 F capacitor. DO NOT leave this pin open.
20149132
FIGURE 2. Simple, low component count reference biasing. Because of the ladder and external resistor tolerances,
the reference voltage of this circuit can vary too much for some applications.
ADC08200QML
www.national.com
11
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