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參數(shù)資料
| 型號： | 5962-0423101QXA |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT RESISTANCE LADDER ADC, PARALLEL ACCESS, CDFP24 |
| 封裝： | CERPACK, DFP-24 |
| 文件頁數(shù)： | 17/17頁 |
| 文件大?。?/td> | 676K |
| 代理商： | 5962-0423101QXA |
Specification Definitions
APERTURE (SAMPLING) DELAY is that time required after
the rise of the clock input for the sampling switch to open.
The Sample/Hold circuit effectively stops capturing the input
signal and goes into the “hold” mode t
AD after the clock goes
high.
APERTURE JITTER is the variation in aperture delay from
sample to sample. Aperture jitter shows up as input noise.
CLOCK DUTY CYCLE is the ratio of the time that the clock
wave form is at a logic high to the total time of one clock
period.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
Measured at 200 MSPS with a ramp input.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and
Distortion Ratio, or SINAD. ENOB is defined as (SINAD –
1.76) / 6.02 and says that the converter is equivalent to a
perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency
at which the reconstructed output fundamental drops 3 dB
below its low frequency value for a full scale input.
FULL-SCALE ERROR is a measure of how far the last code
transition is from the ideal 112 LSB below V
RT and is defined
as:
V
max + 1.5 LSB – VRT
where V
max is the voltage at which the transition to the
maximum (full scale) code occurs.
INTEGRAL NON-LINEARITY (INL) is a measure of the
deviation of each individual code from a line drawn from zero
scale (12 LSB below the first code transition) through positive
full scale (12 LSB above the last code transition). The devia-
tion of any given code from this straight line is measured
from the center of that code value. The end point test method
is used. Measured at 200 MSPS with a ramp input.
INTERMODULATION DISTORTION (IMD) is the creation of
additional spectral components as a result of two sinusoidal
frequencies being applied to the ADC input at the same time.
it is defined as the ratio of the power in the second and third
order intermodulation products to the power in one of the
original frequencies. IMD is usually expressed in dBFS.
MISSING CODES are those output codes that are skipped
and will never appear at the ADC outputs. These codes
cannot be reached with any input value.
OUTPUT DELAY is the time delay after the rising edge of
the input clock before the data update is present at the
output pins.
OUTPUT HOLD TIME is the length of time that the output
data is valid after the rise of the input clock.
PIPELINE DELAY (LATENCY) is the number of clock cycles
between initiation of conversion and when that data is pre-
sented to the output driver stage. New data is available at
every clock cycle, but the data lags the conversion by the
Pipeline Delay plus the Output Delay.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the rms value of the input signal at the output to the
rms value of the sum of all other spectral components below
one-half the sampling frequency, not including harmonics or
d.c.
SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or
SINAD) is the ratio, expressed in dB, of the rms value of the
input signal at the output to the rms value of all of the other
spectral components below half the clock frequency, includ-
ing harmonics but excluding d.c.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ-
ence, expressed in dB, between the rms values of the input
signal at the output and the peak spurious signal, where a
spurious signal is any signal present in the output spectrum
that is not present at the input.
TOTAL HARMONIC DISTORTION (THD) is the ratio ex-
pressed in dB, of the rms total of the first nine harmonic
levels at the output to the level of the fundamental at the
output. THD is calculated as
where A
f1 is the RMS power of the fundamental (output)
frequency and A
f2 through Af10 are the RMS power of the
first 9 harmonic frequencies in the output spectrum
ZERO SCALE OFFSET ERROR is the error in the input
voltage required to cause the first code transition. It is de-
fined as
V
OFF =VZT VRB
where V
ZT is the first code transition input voltage.
ADC08200QML
www.national.com
9
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