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參數(shù)資料
| 型號： | 5082-7623-BE200 |
| 英文描述： | 7.6 mm (0.3 inch)/10.9 mm (0.43 inch) Seven Segment Displays |
| 中文描述： | 7.6毫米（0.3英寸）/10.9毫米（0.43英寸），七段顯示器 |
| 文件頁數(shù)： | 48/134頁 |
| 文件大?。?/td> | 1759K |
| 代理商： | 5082-7623-BE200 |
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TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145K
JULY 2000
REVISED AUGUST 2005
48
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
PWM characteristics
Characteristics of the PWMs are as follows:
16-bit registers
Programmable deadband for the PWM output pairs, from 0 to 12
μ
s
Minimum deadband width of 25 ns
Change of the PWM carrier frequency for PWM frequency wobbling as needed
Change of the PWM pulse widths within and after each PWM period as needed
External-maskable power and drive-protection interrupts
Pulse-pattern-generator circuit, for programmable generation of asymmetric, symmetric, and four-space
vector PWM waveforms
Minimized CPU overhead using auto-reload of the compare and period registers
The PWM pins are driven to a high-impedance state when the PDPINTx pin is driven low and
after
PDPINTx
signal qualification. The PDPINTx pin (after qualification) is reflected in bit 8 of the COMCONx register.
PDPINTA pin status is reflected in bit 8 of COMCONA register.
PDPINTB pin status is reflected in bit 8 of COMCONB register.
capture unit
The capture unit provides a logging function for different events or transitions. The values of the selected GP
timer counter is captured and stored in the two-level-deep FIFO stacks when selected transitions are detected
on capture input pins, CAPx (x = 1, 2, or 3 for EVA; and x = 4, 5, or 6 for EVB). The capture unit consists of three
capture circuits.
Capture units include the following features:
One 16-bit capture control register, CAPCONx (R/W)
One 16-bit capture FIFO status register, CAPFIFOx
Selection of GP timer 1/2 (for EVA) or 3/4 (for EVB) as the time base
Three 16-bit 2-level-deep FIFO stacks, one for each capture unit
Three capture input pins (CAP1/2/3 for EVA, CAP4/5/6 for EVB)—one input pin per capture unit. [All inputs
are synchronized with the device (CPU) clock. In order for a transition to be captured, the input must hold
at its current level to meet two rising edges of the device clock. The input pins CAP1/2 and CAP4/5 can also
be used as QEP inputs to the QEP circuit.]
User-specified transition (rising edge, falling edge, or both edges) detection
Three maskable interrupt flags, one for each capture unit
quadrature-encoder pulse (QEP) circuit
Two capture inputs (CAP1 and CAP2 for EVA; CAP4 and CAP5 for EVB) can be used to interface the on-chip
QEP circuit with a quadrature encoder pulse. Full synchronization of these inputs is performed on-chip.
Direction or leading-quadrature pulse sequence is detected, and GP timer 2/4 is incremented or decremented
by the rising and falling edges of the two input signals (four times the frequency of either input pulse).
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 5082-7626 | 功能描述:LED 顯示器和配件 Yellow Univ RDP RoHS:否 制造商:Avago Technologies 顯示器類型:7 Segment 數(shù)位數(shù)量:2 字符大小:7.8 mm x 14.22 mm 照明顏色:Red 波長:628 nm 共用管腳:Common Anode 工作電壓:2.05 V 工作電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 35 C 封裝:Tube |
| 50827650 | 功能描述:LED 顯示器和配件 0.43in Hi Eff Red Ca 7Seg Display RoHS:否 制造商:Avago Technologies 顯示器類型:7 Segment 數(shù)位數(shù)量:2 字符大小:7.8 mm x 14.22 mm 照明顏色:Red 波長:628 nm 共用管腳:Common Anode 工作電壓:2.05 V 工作電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 35 C 封裝:Tube |
| 5082-7650 | 功能描述:LED 顯示器和配件 Red CA LDP 7 Segment RoHS:否 制造商:Avago Technologies 顯示器類型:7 Segment 數(shù)位數(shù)量:2 字符大小:7.8 mm x 14.22 mm 照明顏色:Red 波長:628 nm 共用管腳:Common Anode 工作電壓:2.05 V 工作電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 35 C 封裝:Tube |
| 5082-7650 | 制造商:Avago Technologies 功能描述:LED DISPLAY 0.43" HE RED |
| 5082-7650 | 制造商:Avago Technologies 功能描述:LED DISPLAY 0.43" HE RED |
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