參數資料
型號: 5082-7623-BE200
英文描述: 7.6 mm (0.3 inch)/10.9 mm (0.43 inch) Seven Segment Displays
中文描述: 7.6毫米(0.3英寸)/10.9毫米(0.43英寸),七段顯示器
文件頁數: 34/134頁
文件大?。?/td> 1759K
代理商: 5082-7623-BE200
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145K
JULY 2000
REVISED AUGUST 2005
34
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
DSP CPU core
The TMS320x240xA devices use an advanced Harvard-type architecture that maximizes processing power by
maintaining two separate memory bus structures — program and data — for full-speed execution. This multiple
bus structure allows data and instructions to be read simultaneously. Instructions support data transfers
between program memory and data memory. This architecture permits coefficients that are stored in program
memory to be read in RAM, thereby eliminating the need for a separate coefficient ROM. This, coupled with a
four-deep pipeline, allows the LF240xA/LC240xA devices to execute most instructions in a single cycle. See
the functional block diagram of the 240xA DSP CPU for more information.
TMS320x240xA instruction set
The x240xA microprocessor implements a comprehensive instruction set that supports both numeric-intensive
signal-processing operations and general-purpose applications, such as multiprocessing and high-speed
control.
For maximum throughput, the next instruction is prefetched while the current one is being executed. Because
the same data lines are used to communicate to external data, program, or I/O space, the number of cycles an
instruction requires to execute varies, depending upon whether the next data operand fetch is from internal or
external memory. Highest throughput is achieved by maintaining data memory on chip and using either internal
or fast external program memory.
addressing modes
The TMS320x240xA instruction set provides four basic memory-addressing modes: direct, indirect, immediate,
and register.
In direct addressing, the instruction word contains the lower seven bits of the data memory address. This field
is concatenated with the nine bits of the data memory page pointer (DP) to form the 16-bit data memory address.
Therefore, in the direct-addressing mode, data memory is paged effectively with a total of 512 pages, with each
page containing 128 words.
Indirect addressing accesses data memory through the auxiliary registers. In this addressing mode, the address
of the instruction operand is contained in the currently selected auxiliary register. Eight auxiliary registers
(AR0
AR7) provide flexible and powerful indirect addressing. To select a specific auxiliary register, the auxiliary
register pointer (ARP) is loaded with a value from 0 to 7 for AR0 through AR7, respectively.
scan-based emulation
TMS320x2xx devices incorporate scan-based emulation logic for code-development and hardware-
development support. Scan-based emulation allows the emulator to control the processor in the system without
the use of intrusive cables to the full pinout of the device. The scan-based emulator communicates with the x2xx
by way of the IEEE 1149.1-compatible (JTAG) interface. The x240xA DSPs do not include boundary scan. The
scan chain of these devices is useful for emulation function only.
相關PDF資料
PDF描述
TMP320LC2401APZS DSP CONTROLLERS
5082-7661-CG400 7.6 mm (0.3 inch)/10.9 mm (0.43 inch) Seven Segment Displays
74ACT823LMQB 9-Bit D Flip-Flop
50E-2C-38.0 TRANS PREBIASED PNP 200MW SOT23
500E-3CL-5.5 E Rated Medium Voltage Fuses
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