參數(shù)資料
型號: 4559
廠商: Renesas Technology Corp.
英文描述: SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
中文描述: 單芯片4位微機(jī)的CMOS
文件頁數(shù): 102/148頁
文件大?。?/td> 1732K
代理商: 4559
Rev.1.04
Aug 23, 2007
Page 57 of 146
REJ03B0188-0104
4559 Group
Fig 56. State transition
Fig 57. Set source and clear source of the P flag
Fig 58. Start condition identified example using the
SNZP instruction
B
E
Clock operating mode
f(RING): stop
f(XIN): stop
f(XCIN): operating
Key-on wakeup
(Stabilizing time c )
execution
D
RAM back-up mode
High-speed mode
D
Operation source clock:
f(XCIN)
MR1,MR0
00
MR1,MR0
10
Low-speed mode
execution
Key-on wakeup
(Stabilizing time e )
execution
(Stabilizing time e )
(Stabilizing time c )
CRCK instruction no execution
Stabilizing time a : Microcomputer starts its operation after counting the f(RING) to 1376 times.
Stabilizing time b : Microcomputer starts its operation after counting the f(RING) to (system clock division ratio X 171) times.
Stabilizing time c : Microcomputer starts its operation after counting the f(XIN) to (system clock division ratio X 171) times.
Stabilizing time d : Microcomputer starts its operation after counting the f(XIN) to (system clock division ratio X 171) times.
Stabilizing time e : Microcomputer starts its operation after counting the f(XCIN) to (system clock division ratio X 171) times.
Re
s
e
t
A
execution
Key-on wakeup
(Stabilizing time b )
execution
(Stabilizing time b )
(Stabilizing time a )
Operation state
Operation source clock:
f(RING)
C
execution
Key-on wakeup
(Stabilizing time d )
execution
(Stabilizing time d )
f(RING): stop
f(XIN): stop
f(XCIN): stop
CRCK instruction execution
MR1,MR0
00
MR1,MR0
01
Internal mode
MR
1
,M
R
0
10
MR
1
,M
R
0
01
Notes
EPOF + POF instruction
Key-on wakeup
Timer 3 underflow
Key-on wakeup
Timer 3 underflow
Key-on wakeup
Timer 3 underflow
Key-on wakeup
Timer 3 underflow
EPOF + POF 2 instruction
EPOF + POF 2
instruction
EPOF + POF 2 instruction
execution
1: Selection of the system clock by the clock control registers MR and RG is state retained at power down.
The waiting time to stabilize oscillation at return can be adjustment by setting the clock control registers MR and RG
before transition to the power down state.
and generate the wait time until the oscillation is stabilized, and then, switch the system clock.
6: When the unoperating clock is selected as the system clock, turn it on by the clock control register RG,
If the CRCK instruction is not executed, the ceramic resonator is selected as the main clock f(XIN).
5: When the RC oscillation circuit is used, executing the CRCK instruction is required.
Mainclock (f(XIN)) and Sub-clock (f(XCIN)) are valid.
A ceramic resonator is selected as the main clock (f(XIN)).
4: The state after system is released from reset;
3: Continuous execution of the EPOF instruction and the POF2 instruction is required to go into the RAM back-up state.
2: Continuous execution of the EPOF instruction and the POF instruction is required to go into the clock operating state.
Ceramic resonator
RC oscillation
Operation state
Operation source clock: f(XIN)
Operation state
Operation source clock: f(XIN)
On-chip oscillator
Operation state
Quartz-crystal oscillation
7: The Sub-clock (quartz-crystal oscillation) is operating except in state D.
S
R
Q
Power downflagP
POF or
POF2
instruction
Reset input
Set source
Clear source
System reset
EPOF instruction +
POF or
POF2
instruction
EPOF instruction +
P
Program start
P= “1”
?
Warm start
Cold start
No
T3F =
?
Return from
timer 3 underflow
Return from
external wakeup signal
“1”
Yes
No
SNZT3
instruction
SNZP
instruction
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