參數(shù)資料
型號: 409119X
元件分類: 復(fù)位半導(dǎo)體
英文描述: 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit
中文描述: 集成電路釤CMOS的EEPLD
文件頁數(shù): 31/34頁
文件大小: 691K
代理商: 409119X
PALCE22V10 and PALCE22V10Z Families
31
POWER-UP RESET
The power-up reset feature ensures that all flip-flops will be reset to LOW after the device has been
powered up. The output state will depend on the programmed pattern. This feature is valuable in
simplifying state machine initialization. A timing diagram and parameter table are shown below.
Due to the synchronous operation of the power-up reset and the wide range of ways V
CC
can rise
to its steady state, two conditions are required to ensure a valid power-up reset. These conditions
are:
N
The V
CC
rise must be monotonic.
N
Following reset, the clock input must not be driven from LOW to HIGH until all applicable input
and feedback setup times are met.
Parameter
Symbol
Parameter Description
Max
Unit
t
PR
t
S
t
WL
Power-up Reset Time
1000
ns
Input or Feedback Setup Time
See Swtching
Characteristics
Clock Wdth LOW
t
PR
t
WL
t
S
4 V
V
CC
Power
Registered
Active-Low
Output
Clock
Figure 3. Power-Up Reset Waveform
V
CC
Off
16564E-021
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