參數(shù)資料
型號: 409119X
元件分類: 復位半導體
英文描述: 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit
中文描述: 集成電路釤CMOS的EEPLD
文件頁數(shù): 3/34頁
文件大小: 691K
代理商: 409119X
PALCE22V10 and PALCE22V10Z Families
3
Variable Input/Output Pin Ratio
The PALCE22V10 has twelve dedicated input lines, and each macrocell output can be an I/O pin.
Buffers for device inputs have complementary outputs to provide user-programmable input signal
polarity. Unused input pins should be tied to V
CC
or GND.
Registered Output Configuration
Each macrocell of the PALCE22V10 includes a D-type flip-flop for data storage and
synchronization. The flip-flop is loaded on the LOW-to-HIGH transition of the clock input. In the
registered configuration (S
1
= 0), the array feedback is from Q of the flip-flop.
Combinatorial I/O Configuration
Any macrocell can be configured as combinatorial by selecting the multiplexer path that bypasses
the flip-flop (S
1
= 1). In the combinatorial configuration, the feedback is from the pin.
0 = Programmed EE bit
1 = Erased (charged) EE bit
Figure 1. Output Logic Macrocell Diagram
16564E-004
CLK
S
1
1
1
0
0
0
1
0
1
AR
SP
0
1
I/O
n
S
0
D Q
Q
S
1
0
S
0
0
Output Configuration
Registered/Active Low
0
1
Registered/Active High
1
0
Combinatorial/Active Low
1
1
Combinatorial/Active High
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