參數(shù)資料
型號: 403GC-3BA40C1
元件分類: 復位半導體
英文描述: 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit
中文描述: 32位微處理器
文件頁數(shù): 34/48頁
文件大小: 768K
代理商: 403GC-3BA40C1
IBM PowerPC 403GC
34
SRAM, ROM, or I/O Write Request with Wait and Hold
Bank Register Bit Settings
Notes:
1. WBE2:3 are address bits 30:31 if the bus width is programmed as byte or halfword.
2. See Table 19 for WBE signal definitions based on bus width.
3. WBE signals can be read/write byte enables based on the setting of a control bit in the IOCR. See waveform and
note 3 on page 33.
4. 403GCWait must be programmed to a value
(CSon + WEon + WEoff) and
(CSon + OEon + WEoff).
If Wait > (CSon + WEon) and > (CSon + OEon), then all signals retain the values shown in cycle 4 until the Wait
time expires.
5. If Hold is programmed > 001, all signals retain the values shown in cycle 6 until the Hold timer expires.
SLF
Burst
Mode
Bus
Width
Ready
Enable
Wait
States
CSon
OEon
WEon
WEoff
Hold
Bit 13
Bit 14
Bits 15:16
Bit 17
Bits 18:23
Bit 24
Bit 25
Bit 26
Bit 27
Bits 28:30
0 or 1
0
xx
0
00 0011
0 or 1
0 or 1
0 or 1
0 or 1
001
SysClk
A6:29,
1
WBE2[A30],
WBE3[A31]
R/W
CSx
5
OE
4,5
WBE0:3
2,3,5
D0:31
Address
Valid
Data Out
CSon=0
CSon=1
CSon=0
WEon=0
CSon=1,0
WEon=0,1
CSon=1
WEon=1
Wait + 1 Cycle
Hold
WEoff=1
WEoff=0
1
2
3
4
5
6
7
8
BusError
Error
CSon=0
OEon=0
CSon=1,0
OEon=0,1
CSon=1
OEon=1
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