參數(shù)資料
型號(hào)： 403GC-3BA40C1
元件分類(lèi)： 復(fù)位半導(dǎo)體
英文描述： 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit
中文描述： 32位微處理器
文件頁(yè)數(shù)： 31/48頁(yè)
文件大?。?/td> 768K
代理商： 403GC-3BA40C1
IBM PowerPC 403GC
31
Reset and HoldAck
The following table summarizes the states of signals on output pins when Reset or HoldAck is active.
Note:
1. Signal may be active while HoldAck is asserted, depending on the operation being performed by the 403GC.
BUS WAVEFORMS
The waveforms in this section represent external bus operations, including SRAM and DRAM accesses,
DMA transfers, and external master operations.
Write Byte Enable Encoding
The 403GC provides four write byte enable signals (WBE0:3) to support 8-, 16-, and 32-bit devices, as
shown in Table 19. For an eight-bit memory region, WBE2:3 are encoded as A30:31 and WBE0 is the
byte-enable line. For a 16-bit region, WBE0 is the high-byte enable, WBE1 is the low-byte enable and
WBE2:3 are encoded as A30:31. For a 32-bit region, address bits 6:29 select the word address and
WBE0:3 select data bytes 0:3, respectively.
Table 18. Signal States During Reset or Hold Acknowledge
Signal Names
State When Reset Active
State When HoldAck Active
A6:29
AMuxCAS
BusReq
CAS0:3
Floating
Inactive (low)
Inactive (low)
Inactive (high)
Floating (set to input mode)
Operable (see note 1)
Operable (see note 1)
Operable (see notes 1 and 2)
CS0:3
CS4:7/RAS3:0
D0:31
DMAA0:3
Floating
Floating
Floating
Inactive (high)
Floating
CS floating, RAS operable (notes 1 and 2)
Floating (external master drives bus)
Inactive (high)
XAck
DRAMOE
DRAMWE
Inactive (high)
Inactive (high)
Inactive (high)
Operable (see note 1)
Operable (see notes 1 and 2)
Operable (see notes 1 and 2)
Error
HoldAck
OE
Reset
Inactive (low)
Inactive (low)
Floating
Floating unless initiating system reset
Operable (see note 1)
Active
Floating (input for XSize1)
Floating unless initiating system reset
R/W
TC0:2
TC3
TDO
Floating
Floating (set to input)
Floating (set to input)
Floating
Floating (set to input)
Inactive (high)
Floating (input for XSize0)
Operable (see note 1)
TS0:6
WBE0:3
XmitD
Inactive (low)
Floating
Inactive (high)
Operable (see note 1)
Operable (inputs for A4:5, A30:31)
Operable (see note 1)
相關(guān)PDF資料
PDF描述
403GCX-3BC50C2 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit
403GCX-3BC66C2 32-Bit Microprocessor
403GCX-3BC80C2 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit
403GCX-3BC80C2A 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit
403GCX-3JC50C2 32-Bit Microprocessor
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
403GCX2JC66C2 制造商:IBM 功能描述:38R2233
403GCX-3BC50C2 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:32-Bit Microprocessor
403GCX-3BC66C2 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:32-Bit Microprocessor
403GCX-3BC80C2 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:32-Bit Microprocessor
403GCX-3BC80C2A 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:32-Bit Microprocessor
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