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參數(shù)資料
| 型號： | 403GC-3BA40C1 |
| 元件分類： | 復(fù)位半導(dǎo)體 |
| 英文描述： | 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit |
| 中文描述： | 32位微處理器 |
| 文件頁數(shù)： | 14/48頁 |
| 文件大?。?/td> | 768K |
| 代理商： | 403GC-3BA40C1 |
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IBM PowerPC 403GC
14
Reset
91
I/O
Reset. A logic 0 input placed on this pin for eight SysClk cycles
causes the 403GC to begin a system reset. When a system reset is
invoked, the Reset pin becomes a logic 0 output for eight SysClk
cycles.
R/W
127 C11
I/O
Read / Write. When the 403GC is bus master, R/W is an output
which is high when data is read from memory and low when data is
written to memory.
When the 403GC is not bus master, R/W is an input from the exter-
nal bus master which indicates the direction of data transfer.
SerClk
26
J1
I
Serial Port Clock. Through the Serial Port Clock Source bit in the
Input/Output Configuration register (IOCR), users may choose the
serial port clock source from either the input on the SerClk pin or
processor SysClk. The maximum allowable input frequency into Ser-
Clk is half the SysClk frequency.
SysClk
22
G3
I
SysClk is the processor system clock input. SysClk supports a 50/50
duty cycle clock input at the rated chip frequency.
TCK
6
D2
I
JTAG Test Clock Input. TCK is the clock source for the 403GC test
access port (TAP). The maximum clock rate into the TCK pin is one
half of the processor SysClk clock rate.
TDI
8
D1
I
Test Data In. The TDI is used to input serial data into the TAP. When
the TAP enables the use of the TDI pin, the TDI pin is sampled on
the rising edge of TCK and this data is input to the selected TAP shift
register.
TDO
16
F3
O
Test Data Output. TDO is used to transmit data from the 403GC TAP.
Data from the selected TAP shift register is shifted out on TDO.
TestA
23
H1
I
Reserved for manufacturing test. Tied low for normal operation.
TestB
24
H2
I
Reserved for manufacturing test. Tied high for normal operation.
TestC/Hold-
Pri
37
M1
I
TestC. Reserved for manufacturing test during the reset interval.
While Reset is active, this signal should be tied low for normal oper-
ation.
HoldReq Priority. When Reset is not active, this signal is sampled to
determine the priority of the external bus master signal HoldReq. If
HoldPri = 0 then the HoldReq signal is considered high priority, oth-
erwise HoldReq is considered low priority.
TestD
38
M3
I
Reserved for manufacturing test. Tied low for normal operation.
TimerClk
25
H4
I
Timer Facility Clock. Through the Timer Clock Source bit in the
Input/Output Configuration register (IOCR), users may choose the
clock source for the Timer facility from either the input on the Timer-
Clk pin or processor CoreClk. The maximum input frequency into
TimerClk is half the CoreClk frequency.
Table 4. 403GC Signal Descriptions
Signal
Name
Pin
Ball
I/O
Type
Function
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| 403GCX-3BC80C2A | 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| 403GCX2JC66C2 | 制造商:IBM 功能描述:38R2233 |
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| 403GCX-3BC66C2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| 403GCX-3BC80C2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| 403GCX-3BC80C2A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
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