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參數(shù)資料
| 型號(hào)： | 403GC-3BA40C1 |
| 元件分類： | 復(fù)位半導(dǎo)體 |
| 英文描述： | 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit |
| 中文描述： | 32位微處理器 |
| 文件頁數(shù)： | 13/48頁 |
| 文件大小： | 768K |
| 代理商： | 403GC-3BA40C1 |
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IBM PowerPC 403GC
13
GND
90
K13
Ground. All ground pins must be used.
101 G12
Ground. All ground pins must be used.
102 H12
Ground. All ground pins must be used.
111 E12
Ground. All ground pins must be used.
121 G8
Ground. All ground pins must be used.
130 B10
Ground. All ground pins must be used.
141 C7
Ground. All ground pins must be used.
150 A5
Ground. All ground pins must be used.
Halt
9
D4
I
Halt from external debugger, active low.
HoldAck
134 B9
O
Hold Acknowledge. HoldAck outputs a logic 1 when the 403GC
relinquishes its external buses to an external bus master. HoldAck
outputs a logic 0 when the 403GC regains control of the bus.
HoldReq
14
F2
I
Hold Request. External bus masters can request the 403GC bus by
placing a logic1 on this pin. The external bus master relinquishes the
bus to the 403GC by deasserting HoldReq.
INT0
31
K3
I
Interrupt 0. INT0 is an interrupt input to the 403GC and users may
program the pin to be either edge-triggered or level-triggered and
may also program the polarity to be active high or active low. The
IOCR contains the bits necessary to program the trigger type and
polarity.
INT1
32
K2
I
Interrupt 1. See description of INT0.
INT2
33
K4
I
Interrupt 2. See description of INT0.
INT3
34
L1
I
Interrupt 3. See description of INT0.
INT4
35
L3
I
Interrupt 4. See description of INT0.
IVR
39
Interface voltage reference. When connected to 3.3V supply, allows
the device to interface to an exclusively 3V system. When connected
to 5V supply, allows the device to interface to 5V or mixed 3V/5V
system. If any input or output connects to 5V system, this pin must
be connected to 5V supply.
OE/XSize1
126 B11
O/I
Output Enable / External Master Transfer Size 1. When the 403GC
is bus master, OE enables the selected SRAMs to drive the data
bus. The timing parameters of OE relative to the chip select, CS, are
programmable via bits in the 403GC bank registers.
When the 403GC is not bus master, OE/XSize1 is used as one of
two external transfer size input bits, XSize0:1.
Ready
13
E4
I
Ready. Ready is used to insert externally generated (device-paced)
wait states into bus transactions. The Ready pin is enabled via the
Ready Enable bit in 403GC bank registers.
RecvD
27
J3
I
Serial Port Receive Data.
Table 4. 403GC Signal Descriptions
Signal
Name
Pin
Ball
I/O
Type
Function
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PDF描述 |
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| 403GCX-3BC50C2 | 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit |
| 403GCX-3BC66C2 | 32-Bit Microprocessor |
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| 403GCX-3BC80C2A | 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit |
| 403GCX-3JC50C2 | 32-Bit Microprocessor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 403GCX2JC66C2 | 制造商:IBM 功能描述:38R2233 |
| 403GCX-3BC50C2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| 403GCX-3BC66C2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| 403GCX-3BC80C2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| 403GCX-3BC80C2A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
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