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參數(shù)資料
| 型號： | 33742 |
| 廠商： | Motorola, Inc. |
| 元件分類： | CAN |
| 英文描述： | System Basis Chip (SBC) with Enhanced High-Speed CAN Transceiver |
| 中文描述： | 系統(tǒng)基礎(chǔ)芯片的增強(qiáng)型（SBC）的高速CAN收發(fā)器 |
| 文件頁數(shù)： | 39/52頁 |
| 文件大小： | 1087K |
| 代理商： | 33742 |
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33742
39
Mode Control Register (MCR)
Tables 10
through
12
describe various Mode Control
Register information.
——————————————————
Table 10. Mode Control Register
MCR
R/W
D3
D2
D1
D0
$000b
W
–
MCTR2
MCTR1
MCTR0
R
BATFAIL
(Note 49)
VDDTEMP
GFAIL
WDRST
Reset
Value
–
–
0
0
0
Reset
Condition
(Write)
(Note 50)
–
–
POR,
RESET
POR,
RESET
POR,
RESET
Notes
49.
BATFAIL bit cannot be set by SPI. BATFAIL is set when V
SUP
falls below 3.0 V.
See
Table 8
, page 38, for definitions of reset conditions.
50.
Table 11. Mode Control Register Control Bits
MCTR2
MCTR
1
MCTR
0
33742 Mode
Description
0
0
0
Enter/Exit
Debug Mode
To enter/exit Debug
Mode, refer to detailed
description in
Debug
Mode: Hardware and
Software Debug with
the 33742
, page 25.
0
0
1
Normal
–
0
1
0
Standby
–
0
1
1
Stop,
Watchdog OFF
(Note 51)
–
0
1
1
Stop,
Watchdog ON
(Note 51)
–
1
0
0
Sleep
(Note 52)
–
1
0
1
Normal
No Watchdog running.
Debug Mode.
1
1
0
Standby
1
1
1
Stop
Notes
51.
52.
Watchdog ON or OFF depends on RCR bit D3.
Before entering Sleep mode, bit BATFAIL in MCR must be
previously cleared (MCR read operation), and bit NOSTOP in
RCR must be previously set to 1.
Table 12. Mode Control Register Status Bits
Name
Value
Description
BATFAIL
0
V
SUP
was not below V
BF
.
1
V
SUP
has been below V
BF
.
VDDTEMP
0
No overtemperature pre-warning.
1
Temperature pre-warning on V
DD
regulator (bit latched).
GFAIL
0
No failure.
1
CAN Failure or HS overtemperature or
V2 low.
WDRST
0
No watchdog reset occurred.
1
Watchdog reset occurred.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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