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參數(shù)資料
| 型號： | 33742 |
| 廠商： | Motorola, Inc. |
| 元件分類： | CAN |
| 英文描述： | System Basis Chip (SBC) with Enhanced High-Speed CAN Transceiver |
| 中文描述： | 系統(tǒng)基礎(chǔ)芯片的增強(qiáng)型（SBC）的高速CAN收發(fā)器 |
| 文件頁數(shù)： | 35/52頁 |
| 文件大?。?/td> | 1087K |
| 代理商： | 33742 |
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33742
35
Detection Principle
In the recessive state, if one of the two bus lines is shorted to
GND, V
DD
,
or V
SUP
, then voltage at the other line follows the
shorted line due to bus termination resistance and the high
impedance of the driver. For example, if CANL is shorted to
GND, CANL voltage is zero, and CANH voltage, as measured
by the Hg comparator, is also close to zero.
In the recessive state the failure detection to GND or V
SUP
is
possible. However, it is impossible to distinguish which bus line,
CANL or CANH, is shorted to GND or V
SUP
. In the dominant
state, the complete diagnostic is possible once the driver is
turned on.
CAN Bus Failure Reporting
CANL bus line failures (for example, CANL short to GND) is
reported in the SPI register TIM1/2. CANH bus line (for
example, CANH short to V
SUP
) is reported in the LPC register.
In addition CANF and CAN-UF bits in the CAN register
indicate that a CAN bus failure has been detected.
Non-Identified and Fully Identified Bus Failures
As indicated in
Table 6
, page 34, when the bus is in a
recessive state it is possible to detect an error condition;
however, is it not possible to fully identify which error. This is
called “non-identified” or “under-acquisition” bus failure. If there
is no communication (i.e., bus idle), it is still possible to warn the
MCU that the device has started to detect a bus failure.
In the CAN register, bits D2 and D1 (CAN-F and CAN-UF,
respectively) are used to signal bus failure. Bit D2 reports a bus
failure and bit D1 indicates if the failure is identified or not (bit
D1 is set to 1 if the error is not identified).
When the detection mechanism is complete, the error will be
fully detected and reported in the TIM1/2 and LPC registers and
bit D1 will be reset to 0.
Number of Samples for Proper Failure Detection
The failure detector requires at least one cycle of recessive
and dominant state to properly recognize the bus failure. The
error will be fully detected after five cycles of recessive-
dominant states. As long as the failure detection circuitry has
not detected the same error for five recessive-dominant cycles,
the bit “non-identified failure” (CAN-UF) will be set.
RXD Permanent Recessive Failure
The purpose of this detection mechanism is to diagnose an
external hardware failure at the RXD output terminal and to
ensure that a permanent failure at the RXD terminal does not
disturb network communication.
In the event RXD is shorted to
a permanent high level signal (i.e., 5.0 V), the CAN protocol
module within the MCU cannot receive any incoming message.
Additionally, the CAN protocol module cannot distinguish the
bus idle state and could start communication at any time. To
prevent this, an RXD failure detection, as illustrated in
Figure 22
and explained below, is necessary.
Figure 22. RXD Path and RXD Permanent Recessive Detection Principle
RXD Failure Detection
The 33742 senses the RXD output voltage at each LOW-to-
HIGH transition of the differential receiver. Excluding internal
propagation delay, RXD output should be LOW when the
differential receiver is LOW. In the event RXD is shorted to
5.0 V (e.g., to V
DD
), RXD will be tied to a high level and the RXD
short to 5.0 V can be detected at the next LOW-to-HIGH
transition of the differential receiver. Compete detection
requires three samples.
When the error is detected, the flag is latched and the CAN
driver is disabled. The error is reported through the SPI register
LPC, bit RXPR.
Recovery Condition
The internal recovery is completed by the sampling of a
correct low level at TXD, as illustrated in
Figure 23
, page 36.
As soon as the RXD permanent recessive is detected, the
RXD driver is deactivated and a weak pulldown current source
CANH
CANL
Diff
V
DD
RXD Sense
RXD
Driver
RXD
TXD
TXD
Driver
60
V
DD
Logic
Diag
CANL
CANH
Diff Output
RXD Output
RXD Short to V
DD
Prop Delay
RXD Flag
RXD Flag Latched
2.0 V
Sampling
Sampling
Sampling
Sampling
Note
RXD Flag is neither the RXPR bit in the LPC register nor the
CAN
-
F
bit in the INTR register.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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