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參數(shù)資料
| 型號： | 33742 |
| 廠商： | Motorola, Inc. |
| 元件分類： | CAN |
| 英文描述： | System Basis Chip (SBC) with Enhanced High-Speed CAN Transceiver |
| 中文描述： | 系統(tǒng)基礎(chǔ)芯片的增強(qiáng)型（SBC）的高速CAN收發(fā)器 |
| 文件頁數(shù)： | 24/52頁 |
| 文件大?。?/td> | 1087K |
| 代理商： | 33742 |
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33742
24
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Forced Wake-Up
The 33742 can wake up automatically after a predetermined
time spent in Sleep or Stop mode. Cyclic Sense and Forced
Wake-up are exclusive. If Forced Wake-Up is enabled (FWU bit
set to 1 in the LPC register), Cyclic Sense cannot be enabled.
CAN Interface Wake-Up
The 33742 incorporates a high-speed 1.0 Mbps CAN
physical interface. It is compatible with ISO 11898-2. The
control of the CAN physical interface operation is accomplished
through the SPI. CAN modes are independent of the 33742
operation modes.
The 33742 can wake up from a CAN message if the CAN
wake-up is enabled. Refer to the section titled
CAN BUS
MODULE DESCRIPTION
beginning on page 29 for details of
the wake-up detection.
SPI Wake-Up
The 33742 can be awakened by the
CS
terminal in Sleep or
Stop modes. Wake-up is detected by the
CS
terminal transition
from LOW to HIGH level. In Stop mode, this corresponds with
the condition where the MCU and the 33742 are in Stop mode
and when the application wake-up event comes through the
MCU.
33742 Power-Up and 33742 Wake-Up from Sleep Mode
After device or system power-up, or after the 33742 wakes
up from Sleep mode, the 33742 enters into the Reset mode
prior to moving into Normal Request mode.
Figure 10
shows the device state diagram and
Figure 11
,
page 25, shows device behavior after power-up sequence.
Figure 10. 33742 State Diagram (Not Valid in Debug Modes)
TiWachdog
(V
DD
High Temperature OR [V
DD
Low > 100 ms & V
SUP
> BFew]) & Nostop & !BATFAIL
Watchdog: Timeout & Nostop & !BATFAIL
Power
Down
Reset
Normal Request
Stop
Sleep
Reset Counter (3.4 ms)
Expired
3
Low OR Watchdog:
Timeout 350 ms & Nostop
1
W
SPI: Standby and
Watchdog Trigger
(Note 42)
3
S
S
SPI: Stop & CS
LOW to HIGH
Transition
SP:Sop&CSLowto
HghTanston
4
2
Watchdog: Timeout OR V
DD
Low
N
S
t
N
&
T
1
Watchdog: Timeout OR V
DD
Low
1
2
Wachdog Tmeou ORV
DD
Low
(Noe43
1
Wake-Up
1
2
3
4
Denotes priority
State Machine Description
Nostop = Nostop bit = 1
!Nostop = Nostop bit = 0
BATFAIL = Batfail bit = 1
!BATFAIL = Batfail bit = 0
V
DD
Overtemperature = V
DD
thermal shutdown occurs
V
DD
LOW = V
DD
below reset threshold
V
DD
LOW > 100 ms = V
DD
below reset threshold for more than 100 ms
Watchdog: Trigger = TIM1 subregister write operation
V
SUP
> BFew = V
SUP
> Battery Fail Early Warning (6.1 V typical)
Watchdog: Timeout = TIM1 register not written before watchdog timeout period
expired, or watchdog written in incorrect time window if watchdog window
selected (except Stop mode). In Normal Request mode, timeout is 355 ms
p2.2 (350 ms p3) ms.
SPI: Sleep = SPI write command to MCR register, data sleep
SPI: Stop = SPI write command to MCR register, data stop
SPI: Normal = SPI write command to MCR register, data normal
SPI: Standby = SPI write command to MCR register, data standby
Normal
Standby
Notes
42.
43.
These two SPI commands must be sent consecutively in this sequence.
If watchdog activated.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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