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| 型號(hào)： | 28F200BX-T |
| 廠商： | Intel Corp. |
| 英文描述： | Evaluation Kit for the MAX608 |
| 中文描述： | 28F200BX -筆- 2兆位（128K的× 16。256K × 8）啟動(dòng)塊閃存系列 |
| 文件頁數(shù)： | 13/55頁 |
| 文件大?。?/td> | 636K |
| 代理商： | 28F200BX-T |
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E
2.0
2-MBIT SmartVoltage BOOT BLOCK FAMILY
13
SEE NEW DESIGN RECOMMENDATIONS
PRODUCT DESCRIPTION
2.1
Memory Blocking Organization
This product family features an asymmetrically-
blocked architecture providing system memory
integration. Each erase block can be erased
independently of the others up to 100,000 times for
commercial temperature or up to 10,000 times for
extended temperature. The block sizes have been
chosen to optimize their functionality for common
applications of nonvolatile storage. The combination
of block sizes in the boot block architecture allow
the integration of several memories into a single
chip. For the address locations of the blocks, see
the memory maps in Figures
4 and 5.
2.1.1
ONE 16-KB BOOT BLOCK
The boot block is intended to replace a dedicated
boot PROM in a microprocessor or microcontroller-
based system.
The 16-Kbyte (16,384 bytes) boot
block is located at either the top (denoted by -T
suffix) or the bottom (-B suffix) of the address map
to accommodate different microprocessor protocols
for boot code location. This boot block features
hardware controllable write-protection to protect the
crucial microprocessor boot code from accidental
modification. The protection of the boot block is
controlled using a combination of the V
PP
, RP#, and
WP# pins, as is detailed in Section
3.4.
2.1.2
TWO 8-KB PARAMETER BLOCKS
The boot block architecture includes parameter
blocks to facilitate storage of frequently updated
small parameters that would normally require an
EEPROM. By using software techniques, the byte-
rewrite functionality of EEPROMs can be emulated.
These techniques are detailed in Intel’s application
note AP-604, Using Intel’s Boot Block Flash
Memory Parameter Blocks to Replace EEPROM
.
Each boot block component contains two parameter
blocks of 8 Kbytes (8,192 bytes) each. The
parameter blocks are not write-protectable.
2.1.3
ONE 96-KB + ONE 128-KB MAIN
BLOCK
After the allocation of address space to the boot
and parameter blocks, the remainder is divided into
main blocks for data or code storage. Each 2-Mbit
device contains one 96-Kbyte (98,304 byte) block
and one 128-Kbyte (131,072 byte) block. See the
memory maps for each device for more information.
相關(guān)PDF資料 |
PDF描述 |
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| 28F200BL-TB | 2-MBIT (128K x 16, 256K x 8)LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 28F200BX-T/B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| 28F200BX-TB | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:2-MBIT (128K x 16, 256K x 8) BOOT BLOCK FLASH MEMORY FAMILY |
| 28F200BX-TL/BL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| 28F200CV-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
| 28F200CV-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
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