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參數(shù)資料
| 型號： | 24WC02 |
| 英文描述： | 1K/2K/4K/8K/16K-Bit Serial E2PROM |
| 中文描述： | 1K/2K/4K/8K/16K-Bit串行E2PROM |
| 文件頁數(shù)： | 3/9頁 |
| 文件大?。?/td> | 45K |
| 代理商： | 24WC02 |
CAT24WC01/02/04/08/16
3
Doc. No. 25051-00 3/98 S-1
A.C. CHARACTERISTICS
V
CC
= +1.8V to +6.0V, unless otherwise specified.
Read & Write Cycle Limits
Symbol
Parameter
1.8V, 2.5V
4.5V-5.5V
Min.
Max.
Min.
Max.
Units
F
SCL
T
I(1)
Clock Frequency
100
400
kHz
Noise Suppression Time
Constant at SCL, SDA Inputs
200
200
ns
t
AA
SCL Low to SDA Data Out
and ACK Out
3.5
1
μ
s
t
BUF(1)
Time the Bus Must be Free Before
a New Transmission Can Start
4.7
1.2
μ
s
t
HD:STA
Start Condition Hold Time
4
0.6
μ
s
μ
s
μ
s
μ
s
t
LOW
Clock Low Period
4.7
1.2
t
HIGH
Clock High Period
4
0.6
t
SU:STA
Start Condition Setup Time
(for a Repeated Start Condition)
4.7
0.6
t
HD:DAT
Data In Hold Time
0
0
ns
t
SU:DAT
t
R(1)
t
F(1)
Data In Setup Time
50
50
ns
SDA and SCL Rise Time
1
0.3
μ
s
SDA and SCL Fall Time
300
300
ns
t
SU:STO
Stop Condition Setup Time
4
0.6
μ
s
t
DH
Data Out Hold Time
100
100
ns
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
Write Cycle Limits
Symbol
Parameter
Min.
Typ.
Max
Units
t
WR
Write Cycle Time
10
ms
Power-Up Timing
(1)(2)
Symbol
Parameter
Max.
Units
t
PUR
t
PUW
Power-up to Read Operation
Power-up to Write Operation
1
1
ms
ms
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| 24WC32P | 制造商:CATALYST 功能描述: |
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