1
CAT24WC01/02/04/08/16
1K/2K/4K/8K/16K-Bit Serial E
2
PROM
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I
2
C Bus Protocol.
PIN CONFIGURATION
DIP Package (P)
BLOCK DIAGRAM
PIN FUNCTIONS
Pin Name
Function
A0, A1, A2
Device Address Inputs
SDA
Serial Data/Address
SCL
Serial Clock
WP
Write Protect
V
CC
+1.8V to +6.0V Power Supply
V
SS
Ground
24WCXX F03
SOIC Package (J)
5020 FHD F01
FEATURES
I
400 KHZ I
2
C Bus Compatible*
I
1.8 to 6.0Volt Operation
I
Low Power CMOS Technology
I
Write Protect Feature
— Entire Array Protected When WP at V
IH
I
Page Write Buffer
DESCRIPTION
I
Self-Timed Write Cycle with Auto-Clear
I
1,000,000 Program/Erase Cycles
I
100 Year Data Retention
I
8-pin DIP, 8-pin SOIC or 8 pin TSSOP
I
Commercial, Industrial and Automotive
Temperature Ranges
The CAT24WC01/02/04/08/16 is a 1K/2K/4K/8K/16K-
bit Serial CMOS E
2
PROM internally organized as 128/
256/512/1024/2048 words of 8 bits each. Catalyst’s
advanced CMOS technology substantially reduces de-
vice power requirements. The the CAT24WC01/02/04/
08/16 feature a 16-byte page write buffer. The device
operates via the I
2
C bus serial interface, has a special
write protection feature, and is available in 8-pin DIP, 8-
pin SOIC or 8-pin TSSOP.
1999 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
8
7
6
5
VCC
WP
SCL
SDA
A2
A0
A1
VSS
1
2
3
4
TSSOP Package (U)
(* Available for 24WC01 and 24WC02 only)
DOUT
ACK
SENSE AMPS
SHIFT REGISTERS
CONTROL
LOGIC
WORD ADDRESS
BUFFERS
START/STOP
LOGIC
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
E
2
PROM
VCC
EXTERNAL LOAD
COLUMN
DECODERS
XDEC
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
VSS
WP
SCL
A0
A1
A2
SDA
A2
A0
A1
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
A0
A1
A2
VCC
WP
SCL
SDA
1
2
3
4
8
7
6
5
VSS
Doc. No. 25051-00 3/98 S-1