參數(shù)資料
型號: 24LC256-IT/MS
元件分類: PROM
英文描述: 32K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8
封裝: ROHS COMPLIANT, PLASTIC, MSOP-8
文件頁數(shù): 4/42頁
文件大?。?/td> 797K
代理商: 24LC256-IT/MS
24AAXX/24LCXX/24FCXX
DS21930C-page 12
2007 Microchip Technology Inc.
5.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end-of-
data to the slave by not generating an Acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (24XX) will leave the data line
high to enable the master to generate the Stop
condition (Figure 5-2).
FIGURE 5-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
FIGURE 5-2:
ACKNOWLEDGE TIMING
Note:
During a write cycle, the 24XX will not
acknowledge commands.
SCL
SDA
(A)
(B)
(D)
(A)
(C)
Start
Condition
Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
SCL
9
8
7
6
5
4
3
2
1
123
Transmitter must release the SDA line at this point,
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
Receiver must release the SDA line
at this point so the Transmitter can
continue sending data.
Data from transmitter
SDA
Acknowledge
bit
Data from transmitter
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