
8
Configuring the élanSC300 Device’s Internal CGA Controller for a Specific LCD Panel
that the élanSC300 microcontroller can support is
2 · 65,536 = 131,072 pixels.
For example: a 640 x 400 LCD display has
640 · 400 = 256,000 pixels. Therefore the
élanSC300 microcontroller will support this resolu-
tion LCD if configured for four banks of memory.
5. If the LCD panel meets the criteria listed in the pre-
vious four steps, then the élanSC300 microcontrol-
ler is capable of driving the LCD panel.
PROGRAMMING THE élanSC300 MICROCONTROLLER TO WORK WITH A
SINGLE-SCREEN LCD PANEL
Before programming the élanSC300 microcontroller to
work with a single-screen LCD panel, the following in-
formation is needed:
I
Display resolution in pixels, W x H (e.g., 640 x 200)
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Mode of operation (i.e., CGA graphics-1 BPP, CGA
graphics-2 BPP, CGA text, HGA graphics-1 BPP,
HGA text)
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If Text mode, the font size (8 x FH for CGA or 9 x FH
for HGA, where FH = font height; 8 x 8 is CGA stan-
dard, 9 x 14 is HGA standard)
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If Graphics mode, the number of 8-Kbyte banks of
memory (see "Steps for Determining if a Single-
Screen LCD Panel can be Driven by the élanSC300
Microcontroller" on page 7)
Determine the Video Index Values to Be
Programmed
First determine the Video Index values for Video In-
dexes 00
–
0Fh, based on the information listed in the
four items above.
CGA & HGA Graphics Mode Values
I
(HT = W · BPP ÷ 16)
The Horizontal Total Register (Index 00H) and Hor-
izontal Displayed Register (Index 01H) are pro-
grammed with the number of 16-bit words per
display row. In 2-color mode (1 BPP), this equals
the width of the display in pixels divided by 16. In 4-
color mode (2 BPP), this equals two times the width
of the display in pixels divided by 16. For example,
a 320 x 240 display is 320 pixels wide. Therefore, in
2-color mode (1 BPP), HT = 320 ÷ 16 = 20 (14h).
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(VT = H ÷ BANKS)
The Vertical Total Register (Index 04H), Vertical
Display Register (Index 06H), and Vertical Sync Po-
sition Register (Index 07H) are programmed with
the value of the height of the display in pixels, di-
vided by the number of banks of memory. For exam-
ple, a 320 x 240 display is 240 pixels high. If four
banks of memory are going to be used, then VT =
240 ÷ 4 = 60 (3Ch).
I
(MSL = BANKS
–
1)
The Max Scan Line Register (Index 09H) is pro-
grammed with the number of banks of memory to
be used, minus 1. If four banks of memory are going
to be used, then MSL = 4 – 1 = 3.
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(SAH) (SAL)
The Start Address High (Index 0CH) and Start Ad-
dress Low (Index 0DH) Video Indexes together
form a 14-bit offset (bits 7 and 6 of Index 0CH are
not used) that determines the location in video
memory where the video controller will start fetching
data to be displayed on the screen. Typically, these
indexes will be set to 0 so the display data starts
being fetched from B8000h. Scrolling can be imple-
mented by changing the values in these registers.
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All the other index registers (02, 03, 05, 08, 0Ah,
0Bh, 0Eh, 0Fh) will be programmed with 0h.
CGA & HGA Text Mode Values
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HT = W · BPP ÷ 16
The Horizontal Total Register (Index 00H) and Hor-
izontal Displayed Register (Index 01H) are pro-
grammed with the number of characters per row.
The character width is hard coded to be 8 pixels
wide. Therefore, HT is the width of the display in pix-
els divided by 8. For example, a 320 x 240 display
is 320 pixels wide. Therefore HT = 320 ÷ 8 = 40
(28h).
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(VT = H ÷ Y)
The Vertical Total Register (Index 04H), Vertical
Displayed Register (06H), and Vertical Sync Posi-
tion Register (07H) are programmed with the value
of the number of rows of characters. This is deter-
mined by the height of the display in pixels, divided
by the height of the character in pixels (Y from the
equation below). For example, a 320 x 240 display
is 240 pixels high. If using an 8 x 10 font, then VT =
240 ÷ 10 = 24 (18h).
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(MSL = Y –1)
The Max Scan Line Register (Index 09H) is pro-
grammed with the pixel height of the font – 1. For
example, if using an 8 x 10 font, then MSL =
10 – 1 = 9.