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參數(shù)資料
| 型號： | 20749 |
| 英文描述： | Configuring the ?lanSC300 Device＇s Internal CGA Controller for a Specific LCD Panel |
| 中文描述： | 配置？lanSC300設備的內(nèi)部海巡署控制器，用于特定的液晶面板 |
| 文件頁數(shù)： | 12/26頁 |
| 文件大小： | 277K |
| 代理商： | 20749 |
12
Configuring the élanSC300 Device’s Internal CGA Controller for a Specific LCD Panel
Using the élanSC300 Microcontroller
Evaluation Board to Test an LCD Panel
The élanSC300 microcontroller evaluation board has a
20-pin header (P18) with all the LCD interface signals
connected to it. The evaluation board provides a –14 V
to –16 V contrast voltage (adjust using VR1) and a –17
V
ee
voltage. If the panel to be tested requires voltages
other than these, a separate circuit will need to be
bread boarded, or an external DC power supply used.
The following evaluation board jumpers and resistor
packs should also be set to configure the evaluation
board for Internal Video mode: JP16 = 1–2; JP18 =
Open; Install RP3 and RP4 (RP1, RP2, RP5, and RP6
must be empty).
Note that the evaluation board BIOS is set up to config-
ure for a 640 x 200 single-panel display when the
élanSC300 microcontroller is in Internal Video mode. If
a panel size other than this is used without modifying
the BIOS, the screen may not display anything at boot-
up. Refer to "LCD Development Tips and Tricks" for in-
structions on how to use CTTY for console activity
while developing a screen application.
Also note that if a dual-screen LCD panel is used, the
SBHE, IRQ14, MCS16, and IOS16 ISA signals are no
longer available outside the chip. This means the stan-
dard 16-bit IDE interface cannot be used.
Table 5 shows how the pins on the 20-pin header
should be connected to the pins of a Hitachi
LMG6272XNFR, 640 x 200 single-panel display.
Table 5.
Pin Connections
The élanSC300 Microcontroller Evaluation Board
P18 Header Pins
Pin #
Pin Name
Function
1
VccLCD5
+5
2
GND
Ground
3
LCDFRM
Frame start
HITACHI: LMG6272XNFR
640 x 200 Single Panel LCD
Pin Name
Function
Vdd
Power supply for logic circuit
Vss
Ground
FLM
The FLM signal indicates the
start of each display cycle
CL1
Data latch
CL2
Data shift
Not used
D0
Data bit 0 (LSB)
D1
Data bit 1
D2
Data bit 2
D3
Data bit 3 (MSB)
Not used
Pin #
10
11
5
=
=
=
4
5
6
7
8
9
LCDCP1
LCDCP2
LCDM
LCDD0
LCDD1
LCDD2
LCDD3
LCDDL0
Line clock
Shift clock
AC modulation
Data bit 0 (LSB)
Data bit 1
Data bit 2
Data bit 3 (MSB)
Dual-screen panel data bit 0 for
lower panel
Dual-screen panel data bit 1 for
lower panel
Dual-screen panel data bit 2 for
lower panel
Dual-screen panel data bit 3 for
lower panel
Adjustable voltage
between –14 V to –16 V
–17 V
Not connected
=
=
7
8
x
1
2
3
4
x
=
=
=
=
10
11
12
LCDDL1
x
Not used
13
LCDDL2
x
Not used
14
LCDDL3
x
Not used
15
Contrast
=
9
Vo
LCD driving voltage
16
Vee
NC
=
12
Vee
Power supply for LC driving
17
—
20
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