參數(shù)資料
型號(hào)： 20749
英文描述： Configuring the ?lanSC300 Device＇s Internal CGA Controller for a Specific LCD Panel
中文描述： 配置？lanSC300設(shè)備的內(nèi)部海巡署控制器，用于特定的液晶面板
文件頁(yè)數(shù)： 20/26頁(yè)
文件大?。?/td> 277K
代理商： 20749
Configuring the élanSC300 Device’s Internal CGA Controller for a Specific LCD Panel
7
Mode of operation
The mode of operation affects the refresh rate of the
display, and when a Graphics mode is selected, deter-
mines the amount of video SRAM required. When the
élanSC300 microcontroller is configured for a Graphics
mode, the 32 Kbyte of memory is divided into four 8-
Kbyte banks. Video Index register 09H controls
whether the display information is divided between just
two or all four of the memory banks.
I
CGA Mode
When CGA mode is selected, the élanSC300 mi-
crocontroller uses a pixel clock frequency of
9.557 MHz. The refresh rate for Text mode, or 2-
color Graphics mode can be calculated by dividing
the pixel clock frequency by the screen resolution
programmed into the video controller, taking into ac-
count the 20 extra pixel clocks per line mentioned
earlier. The refresh rate for 4-color Graphics mode
will be half that value.
I
HGA Mode
When HGA mode is selected, the élanSC300 mi-
crocontroller uses a pixel clock frequency of
14.336 MHz. The refresh rate for Text mode or 2-
color Graphics mode can be calculated by dividing
the pixel clock frequency by the screen resolution
programmed into the video controller, taking into ac-
count the 20 extra pixel clocks per line mentioned
earlier.
STEPS FOR DETERMINING IF A SINGLE-SCREEN LCD PANEL CAN BE DRIVEN BY THE
élanSC300 MICROCONTROLLER
1. Does the panel have a 4-bit data interface
– Yes: Go to step 2.
– No: Panel cannot be driven by the élanSC300
microcontroller.
2. Determine what rate the élanSC300 microcontroller
will refresh the LCD panel. Refresh rate is a factor
of the LCD panel resolution and pixel clock fre-
quency, which is determined by the mode of opera-
tion. For a panel size of W x H, and a bits-per-pixel
value of BPP (1 or 2), the refresh rate will be as fol-
lows:
(pixel clock frequency) ÷ ((W + 20) · BPP · H)
In CGA mode, the pixel clock frequency is
9.557 MHz. In HGA mode the pixel clock frequency
is 14.336 MHz. Therefore, when the élanSC300 mi-
crocontroller is configured for a 320 x 240, 1-BPP
resolution LCD in CGA mode, the refresh rate is
9.557 MHz ÷ (340 · 1 · 240) = 117 Hz. When the
élanSC300 microcontroller is configured for the
same size display in HGA mode, the refresh rate is
14.336 MHz ÷ (340 · 1 · 240) = 175 Hz. Note that 2-
color (1 BPP) mode can be supported by either
CGA or HGA, but the HGA refresh rate is approxi-
mately 50% higher.
3. Does the refresh rate fall in the range supported by
the LCD panel
– Yes: Go to step 4.
– No: Panel cannot be driven by the élanSC300
microcontroller.
Note:
If the refresh rate driven by the élanSC300 mi-
crocontroller is too fast for the panel, it is possible to ef-
fectively slow the refresh rate to the panel by
programming the élanSC300 microcontroller’s graph-
ics controller using a logical panel width that is greater
than the physical LCD panel width. If this is done, the
logical panel width must be used for all calculations,
and it should first be tested on the same panel before
making the design choice. This will determine if the
panel can handle the additional shift clocks sent to it as
a result of the larger panel width.
4.
Does the élanSC300 microcontroller support the
LCD panel’s video SRAM requirements
This is a concern only if the LCD will be operated in
a Graphics mode; therefore, Text mode is not dis-
cussed.
2 bits per pixel (four shades of gray)
This mode consumes the most memory. Each bank
of memory is 8 Kbyte (8192 bytes). In 2 BPP mode,
each byte contains the equivalent of 4 pixels of in-
formation. Each bank can store information for
32,768 pixels. Therefore, if configured for 4 banks
of memory, the maximum number of pixels that the
élanSC300 microcontroller can support is 4 ·
32,768 = 131,072 pixels. If configured for two banks
of memory, the maximum number of pixels that the
élanSC300 microcontroller can support is 2 ·
32,768 = 65,536 pixels.
For example: a 320 x 240 LCD display has
320 · 240 = 76,800 pixels. Therefore, the
élanSC300 microcontroller will support this resolu-
tion LCD if configured for four banks of memory.
1 bit per pixel (2 shades of gray)
Each bank of memory is 8 Kbyte (8192 bytes). In
1 BPP mode, each byte contains the equivalent of 8
pixels of information. Each bank can store informa-
tion for 65,536 pixels. Therefore, if configured for
four banks of memory, the maximum number of pix-
els that the élanSC300 microcontroller can support
is 4 · 65,536 = 262,144 pixels. If configured for two
banks of memory, the maximum number of pixels
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