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| 型號： | 20749 |
| 英文描述： | Configuring the ?lanSC300 Device＇s Internal CGA Controller for a Specific LCD Panel |
| 中文描述： | 配置？lanSC300設(shè)備的內(nèi)部海巡署控制器，用于特定的液晶面板 |
| 文件頁數(shù)： | 2/26頁 |
| 文件大?。?/td> | 277K |
| 代理商： | 20749 |
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Configuring the élanSC300 Device’s Internal CGA Controller for a Specific LCD Panel
Pixel Clock
This is the standard unit of measure from which all of
the LCD clocking signals can be derived. The pixel
clock can be loosely defined as the rate at which pixels
are displayed on the screen. On the élanSC300 micro-
controller, the pixel clock used is one of two fixed fre-
quencies: 14.336 MHz for HGA mode or 9.557 MHz
(which is 2/3 of 14.336) for CGA mode. On the
élanSC300 microcontroller, the pixel clock is internal to
the video controller and is not available external to the
chip.
Shift Clock (CP2)
The shift clock, known as the CP2 signal on the
élanSC300 microcontroller, tells the LCD panel when
data is valid on the LCD data bus (the élanSC300 mi-
crocontroller pins LCDD0–LCDD3 and LCDDL0–
LCDDL3). Data is valid on the falling edge of shift clock.
The frequency of the shift clock can be determined by
the pixel clock frequency divided by the number of data
bits per panel. For both single- and dual-screen panels
with the élanSC300 microcontroller, the number of bits
per panel is four. Therefore, the shift clock frequency
will be either 14.336 MHz ÷ 4 data bits = 3.58 MHz, or
9.557 MHz ÷ 4 data bits = 2.389 MHz.
Line Clock (CP1)
The line clock, known as the CP1 signal on the
élanSC300 microcontroller, tells the LCD panel that a
complete row (horizontal line) of pixel data has been
sent to the LCD panel to be displayed. Additional shift
clocks indicate valid data for the next row of pixels (i.e.,
display the current row and prepare to receive pixel
data for the next row).
A line clock pulse will occur once for every row of pixel
data sent to the LCD panel. For example, a 320 x 240
LCD screen has 240 rows; therefore, 240 line clocks
will occur each time the panel is refreshed.
When CP1 is asserted on the élanSC300 microcontrol-
ler’s LCD controller, there is a period of about 20 pixel
clock cycles during which CP2 will not be asserted.
This has a slight effect on the refresh rate as described
later in this document.
Frame Start (FRM)
Frame start, known as FRM on the élanSC300 micro-
controller, is asserted at the start of every frame (panel
scan). This signal tells the LCD panel that the next data
sent to it via the shift clock will be for the top row of the
panel. This signal is sometimes referred to as the FLM
(First Line Marker) signal.
On the élanSC300 microcontroller’s LCD controller,
there is no “dead time” when FRM is asserted. The
FRM assertion overlaps with the normal CP1 assertion
at the end of the last line.
Refresh Rate
The refresh rate of the LCD panel is the number of
times per second the screen is redrawn. This affects
the crispness and brightness of the image on the dis-
play. On the élanSC300 microcontroller, the refresh
rate is affected by the screen resolution programmed
into the video controller, the number of bits per pixel
(BPP) (in Graphics mode only), and the pixel clock fre-
quency.
On the élanSC300 microcontroller, the refresh rate for
Text mode or 2-color Graphics mode can be calculated
by dividing the pixel clock frequency by the screen res-
olution programmed into the video controller, taking
into account the 20 extra pixel clocks per line men-
tioned in the previous section. The refresh rate for 4-
color Graphics mode will be half that amount. For ex-
ample, if the controller is programmed
for a 320 x 240
LCD screen and configured for CGA 2-color mode
(which means that the 9.557 MHz pixel clock is used),
then each line consists of 320 + 20 = 340 pixel clocks,
and the refresh rate would be 9.557 MHz ÷ (340 · 240)
= 117.1 Hz.
If the refresh rate is marginal for the LCD size in CGA
Graphics mode, a 50% increase in refresh rate can be
achieved by using HGA Graphics mode. On the
élanSC300 microcontroller, the selection of CGA or
HGA mode can remain independent of the resolution.
(This is discussed later in this document.)
DC Voltage Biasing
DC voltage biasing is a condition of LCD panels when
the liquid crystals in the display become permanently
aligned. Normally, the liquid crystals are nonaligned, al-
lowing light to pass through the display. When a DC
voltage is applied, the liquid crystals align themselves,
blocking the light from passing through the display. The
effect of this alignment causes a pixel to appear dark
on the display. As a panel becomes DC voltage biased,
the liquid crystals in the display become permanently
aligned, eventually causing the entire display to appear
black. AC modulation (defined in the next section) is
used to prevent DC biasing.
LCD Panel AC Modulation (M)
All LCD panels implement what is known as AC modu-
lation to prevent DC voltage biasing from damaging the
display. AC modulation is accomplished by periodically
reversing the polarity of the DC voltage that is applied
to the liquid crystals. This prevents the crystals from
becoming permanently aligned. Some panels control
the frequency at which the polarity is reversed inter-
nally. Other panels require an outside source to control
this. For panels requiring an outside source to imple-
ment this control, the élanSC300 microcontroller sup-
plies an AC modulation signal, M. This signal can be
programmed to change state once per frame, once
every 13 line clocks, or once every 61 line clocks.
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