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參數(shù)資料
| 型號： | 20575 |
| 英文描述： | Wireless LAN DSSS PC Card Reference Design Application ? 220KB (PDF) |
| 中文描述： | 無線局域網(wǎng)擴頻PC卡參考設(shè)計中的應(yīng)用？欺詐郵件（PDF格式） |
| 文件頁數(shù)： | 21/25頁 |
| 文件大?。?/td> | 220K |
| 代理商： | 20575 |
20
RX Flow
The Am79C930 device will perform the following func-
tions of the RX operation:
I
Enable the RX portion of the HSP3824 chipset
I
Monitor USER6/EXTSDF input for RX Unique Word
detection event as signalled by the HSP3824
I
Parse the PLCP header
I
Check the PLCP CRC16
I
Parse MAC header
I
Pass MAC data to the LLC layer
I
Check the MAC CRC32
I
Disable the RX portion of the HSP3824 chipset
The receive operation is enabled by the host driver soft-
ware. Individual receive events are not generally pre-
dictable. Therefore, the receive operation is initiated by
the Am79C930 firmware whenever the transmit opera-
tion is not in progress, the current power savings state
dictates remaining awake, and the host driver software
has enabled the receive operation. An indication from
the HARRIS PRISM chip will begin the sequence that
constitutes the reception of a frame.
RX SEQUENCE for the Am79C930 Device Gener-
ates and Strips PHY Fields
Note:
Only the interaction between the Am79C930 device
and the HARRIS PRISM subsystem is described.
The steps of the Am79C930 RX operation in the HAR-
RIS PRISM PC CARD application are listed below:
1. The Am79C930 firmware prepares the DMA1 en-
gine for DMA transfers from the RX FIFO to the next
available RX buffer space. The DMA1 engine is en-
abled.
2. The Am79C930 firmware sets the RXS bit of TIR16
to enable the RX state machine whenever there is
no transmit activity (and the current power savings
state allows it). RX data and RX clock from the de-
coder in the HARRIS HSP3824 arrives at the RXD
and RXCIN inputs. The RX DATA will be descram-
bled by the HARRIS HSP3824 device. RX DATA is
not stored by the Am79C930 device until the Unique
Word has been identified by the SFD detection logic
of the Am79C930 device.
3. Once the Unique Word field has been detected, the
Am79C930 device’s RX state machine will move
from the Unique-Word-search state to the DATA-ac-
cept state. The Am79C930 device will now begin
accepting data at the RXD input and placing it into
the RX FIFO.
4. The first bit that is placed into the RX FIFO is the first
bit of the PLCP header.
5. As RX data continues to arrive, the RX FIFO signals
a request for DMA to the embedded 80188. The
DMA machine moves bytes from the RX FIFO to the
RX buffer in the SRAM.
6. If the incoming RX frame is a 2 Mbps frame, then the
bit rate will change from 1 Mbps to 2 Mbps at the
PHY/MAC boundary. At this point, the RX clock from
the HARRIS HSP3824 will switch from 1 MHz to 2
MHz. The Am79C930 device is able to accept any
RX clock rate at any time, up to a limit of 8 MHz.
7. As RX data continues to arrive, the Am79C930 de-
vice firmware examines the data that has been
placed into the SRAM in order to determine the na-
ture of the RX frame. At this time, PLCP header in-
formation is parsed for correct field values and a valid
CRC16. If the CRC16 value is corrupted, then the
firmware will terminate the reception of the frame at
this point by sending a deassertion pulse on the
RX_PE signal.
Note that the HSP3824 contains an OVERRIDE bit
(CR2[5]) to allow the message to continue despite
the presence of a bad PLCP CRC16 indication. This
allows for the Am79C930 firmware to have complete
control of the subsequent action in the case of a bad
CRC16 value.
8. If CRC16 indication is OK, then RX continues. As
the MAC header is received, the Am79C930 firm-
ware continues to parse incoming fields, determines
future actions (such as responding with a transmis-
sion) and prepares for them by copying appropriate
fields of the MAC header into a TX buffer.
9. When PLCP length (obtained from the PLCP head-
er) number of bytes occurs, the Am79C930 firmware
will deassert the RX_PE signal to end the frame re-
ception to reset the RX portion of the HSP3824.
10.End of reception.
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