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| 型號： | 20575 |
| 英文描述： | Wireless LAN DSSS PC Card Reference Design Application ? 220KB (PDF) |
| 中文描述： | 無線局域網(wǎng)擴頻PC卡參考設(shè)計中的應用？欺詐郵件（PDF格式） |
| 文件頁數(shù)： | 13/25頁 |
| 文件大?。?/td> | 220K |
| 代理商： | 20575 |
12
Am79C930 Register Settings
MIR8[1:0] FLASHWAIT[1:0]
The FLASHWAIT bits of MIR8[1:0] should be set to
a value that is appropriate for the FLASH being used
in the design. With a 40-MHz signal at the CLKIN
input, the FLASHWAIT bits are interpreted as follows
in Table 3.
Note:
Am79C930 memory interface bus is two CLKIN peri-
ods in length (i.e., at CLKIN = 40 MHz, then two CLKIN
periods = 2*25 ns = 50 ns.)
Each wait state on the asynchronous
MIR9[5:4] SRAMWAIT[1:0]
The SRAMWAIT bits of MIR9[5:4] should be set to a
value that is appropriate for the SRAM being used in the
design. With a 40-MHz signal at the CLKIN input, the
SRAMWAIT bits are interpreted as follows in Table 4.
Note:
Am79C930 memory interface bus is two CLKIN peri-
ods in length (i.e. at CLKIN = 40 MHz, then two CLKIN
periods = 2 x 25 ns = 50 ns.)
Additional memory parameter restrictions are as follows
with CLKIN = 40 MHz.
Each wait state on the asynchronous
TIR2[2] SDC
TIR2[7:0] should be set to 40h.
The SDC bit of TIR2 determines the polarity of the clock
pulse that will appear on the SDCLK output pin of the
Am79C930 device. A setting of 0 yields a positive going
pulse when the TIR3 register is used for serial commu-
nications. A setting of 1 yields a negative going pulse
when the TIR3 register is used for serial communications.
For RADIO API calls that access the HSP3824, it is
required that the SDC bit of TIR2 be set to 1, in order to
provide the necessary setup and hold time of the serial
data with respect to the serial clock from the Am79C930
device. For RADIO API calls that access other devices
within the PRISM subsystem (such as the HFA3524
dual synthesizer), it is required that the SDC bit of TIR2
be set to 0 in order to provide a positive clock for the
serial data transfer. The switching of the SDC bit of TIR2
from 1 to 0, and vice versa, should occur within the
respective RADIO API calls.
TIR3[7:0] Fast Serial Port
The Fast Serial Port is used for serial communications
with the HSP3824 baseband processor and the
HFA3524 frequency synthesizer devices. The serial
data transferred through this means is used to program
the initial operating state of the HSP3824 device and is
used to program the operating frequencies of the syn-
thesizers in order to tune the radio to the proper channel.
Channel switching is required for periodic scanning op-
erations in order to locate access points for potential
connections, for changing associations from one ac-
cess point to another and for creating
connections. Channel switching is generally automati-
cally performed as part of the MAC management func-
tion and, therefore, is generally transparent to the user.
However, the specific signalling sequence required to
ad hoc
network
Table 3.
Number Of Wait States Created On
Am79c930 Memory Interface Bus
3
2
1
0
FLASHWAIT Bits
FLASHWAIT[1:0] Programmed Value
11 (RESET default)
10
01
00
Maximum Guaranteed tmAA Access
Time Allowed For Flash Device
205 ns
155 ns
105 ns
55 ns
Table 4.
Number Of Wait States Created On
Am79c930 Memory Interface Bus
3
2
1
0
SRAMWAIT Bits
SRAMWAIT[1:0] Programmed Value
11 (RESET default)
10
01
00
Maximum Guaranteed Access tmAA
Time Allowed For SRAM Device
205 ns
155 ns
105 ns
55 ns
Table 5.
Memory Parameter Restrictions with
CLKIN = 40 MHz
Memory Speed
55 ns MAX, t
t
OE
30 ns MAX
105 ns MAX, t
t
OE
80 ns MAX
155 ns MAX, t
t
OE
130 ns MAX
WAIT States
0
t
ACC
CE
55 ns MAX,
t
ACC
CE
105 ns MAX,
1
t
ACC
CE
155 ns MAX,
2
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