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| 型號： | 20575 |
| 英文描述： | Wireless LAN DSSS PC Card Reference Design Application ? 220KB (PDF) |
| 中文描述： | 無線局域網(wǎng)擴頻PC卡參考設(shè)計中的應用？欺詐郵件（PDF格式） |
| 文件頁數(shù)： | 14/25頁 |
| 文件大小： | 220K |
| 代理商： | 20575 |
13
program these devices must be coded into an API in
order to allow the MAC code to be independent of PHY
implementation. Therefore, system integrators will write
API code that accesses TIR3 for the purpose of
executing a channel reprogramming operation. This API
routine will be called at the appropriate time and with
the appropriate arguments by the MAC code. The
HSP3824 and frequency synthesizer programming op-
erations are performed through the TIR3 fast serial port.
There are two other modes for operating the serial com-
munications link with the HSP3824 and frequency syn-
thesizer devices. Both of these modes are controlled
with the bits in the TIR2 register and are slower than the
mode that uses the fast serial port (TIR3 register).
Therefore, the TIR3 method of serial transfer has been
chosen. This minimizes code execution time for API
modules that include serial communications between
the Am79C930 and the PHY-layer devices.
Note:
Am79C930 data sheet. The description in the data sheet
should be used when writing API modules that require
serial communications with the HARRIS devices.
The HARRIS PRISM chip requires the following timing
to appear on the serial port lines during read and write
operations (see Figures 1 and 2, respectively).
The proper use of the TIR3 register is found in the
Figure 1.
HSP3824 Serial Port Timing Diagram (Read Operation)
Figure 2.
HSP3824 Serial Port Timing Diagram (Write Operation)
SDSEL1# (CS)
SDSEL2# (AS)
SDSEL3# (R/W#)
SDCLK (SCLK)
SDDATA (SD)
address
data
don't care
7
6
5
4
3
2
1
7
6
5
4
3
1
0
MSB
MSB
2
SDSEL1# (CS)
SDSEL2# (AS)
SDSEL3# (R/W#)
SDCLK (SCLK)
SDDATA (SD)
address
data
don't care
7
6
5
4
3
2
1
7
6
5
4
3
1
0
MSB
MSB
2
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