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| 型號： | 100-1221-3 |
| 廠商： | Bluetechnix |
| 文件頁數(shù)： | 48/68頁 |
| 文件大小： | 0K |
| 描述： | CORE MOD CM-BF537E 600MHZ CONN |
| 標準包裝： | 1 |
| 模塊/板類型： | 核心模塊 |
| 其它名稱： | 100-1221 100-1221-ND |
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Rev. J
|
Page 52 of 68
|
February 2014
TEST CONDITIONS
All timing parameters appearing in this data sheet were
measured under the conditions described in this section.
Figure 48 shows the measurement point for ac measurements
(other than output enable/disable). The measurement point is
VMEAS = VDDEXT/2.
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to the point when they
start driving. The output enable time tENA is the interval from
the point when a reference signal reaches a high or low voltage
level to the point when the output starts driving as shown in the
Output Enable/Disable diagram (Figure 49). The time tENA_MEA-
SURED is the interval from when the reference signal switches to
when the output voltage reaches 2.0 V (output high) or 1.0 V
(output low). Time tTRIP is the interval from when the output
starts driving to when the output reaches the 1.0 V or 2.0 V trip
voltage. Time tENA is calculated as shown in
the equation:
If multiple pins (such as the data bus) are enabled, the measure-
ment value is that of the first pin to start driving.
Output Disable Time
Output pins are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by V is dependent on the capacitive load, CL, and the
load current, IL. This decay time can be approximated by
the equation:
The output disable time tDIS is the difference between tDIS_MEA-
the interval from when the reference signal switches to when the
output voltage decays V from the measured output-high or
output-low voltage. The time tDECAY is calculated with the test
loads CL and IL, and with V equal to 0.5 V.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose V
to be the difference between the processor’s output voltage and
the input threshold for the device requiring the hold time. A
typical V is 0.4 V. CL is the total bus capacitance (per data line),
and IL is the total leakage or three-state current (per data line).
The hold time is tDECAY plus the minimum disable time (for
example, tDSDAT for an SDRAM write cycle).
Figure 48. Voltage Reference Levels for AC Measurements (Except
Output Enable/Disable)
INPUT
OR
OUTPUT
VMEAS
tENA
tENA_MEASURED tTRIP
–
=
Figure 49. Output Enable/Disable
tDECAY
CL V
I
L
=
REFERENCE
SIGNAL
tDIS
OUTPUT STARTS DRIVING
VOH (MEASURED)
V
VOL (MEASURED) + V
tDIS_MEASURED
VOH
(MEASURED)
VOL
(MEASURED)
VTRIP(HIGH)
VOH(MEASURED)
VOL(MEASURED)
HIGH IMPEDANCE STATE
OUTPUT STOPS DRIVING
tENA
tDECAY
tENA_MEASURED
tTRIP
VTRIP(LOW)
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| 100-1225-1 | 功能描述:CORE MOD TCM-BF537 500MHZ CONN RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器或微處理器模塊 系列:- 產(chǎn)品目錄繪圖:DLP-245SY-G 標準包裝:1 系列:USB 模塊/板類型:開發(fā)板 適用于相關(guān)產(chǎn)品:USB 其它名稱:813-1006 |
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