參數(shù)資料
型號: 100-1221-3
廠商: Bluetechnix
文件頁數(shù): 40/68頁
文件大小: 0K
描述: CORE MOD CM-BF537E 600MHZ CONN
標(biāo)準(zhǔn)包裝: 1
模塊/板類型: 核心模塊
其它名稱: 100-1221
100-1221-ND
Rev. J
|
Page 45 of 68
|
February 2014
Timer Clock Timing
Table 37 and Figure 27 describe timer clock timing.
Timer Cycle Timing
Table 38 and Figure 28 describe timer expired operations. The
input signal is asynchronous in “width capture mode” and
“external clock mode” and has an absolute maximum input fre-
quency of (fSCLK/2) MHz.
Table 37. Timer Clock Timing
Parameter
Min
Max
Unit
Switching Characteristic
tTODP
Timer Output Update Delay After PPI_CLK High
12
ns
Figure 27. Timer Clock Timing
PPI_CLK
TMRx OUTPUT
tTODP
Table 38. Timer Cycle Timing
2.25 V
V
DDEXT 2.70 V
or
0.80 V
V
DDINT 0.95 V
1
2.70 V
V
DDEXT 3.60 V
and
0.95 V
V
DDINT 1.43 V
2, 3
Parameter
Min
Max
Min
Max
Unit
Timing Characteristics
tWL
Timer Pulse Width Input Low (Measured In SCLK Cycles)
4
1 × tSCLK
ns
tWH
Timer Pulse Width Input High (Measured In SCLK Cycles)
1 × tSCLK
ns
tTIS
Timer Input Setup Time Before CLKOUT Low5
5.5
5.0
ns
tTIH
Timer Input Hold Time After CLKOUT Low5
1.5
ns
Switching Characteristics
tHTO
Timer Pulse Width Output (Measured In SCLK Cycles)
1 × tSCLK
(2
32–1) × t
SCLK 1 × tSCLK
(2
32–1) × t
SCLK
ns
tTOD
Timer Output Update Delay After CLKOUT High
6.5
6.0
ns
1 Applies to all nonautomotive-grade devices when operated within either of these voltage ranges.
2 Applies to all nonautomotive-grade devices when operated within these voltage ranges.
3 All automotive-grade devices are within these specifications.
4 The minimum pulse widths apply for TMRx signals in width capture and external clock modes. They also apply to the PF15 or PPI_CLK signals in PWM output mode.
5 Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.
Figure 28. Timer Cycle Timing
CLKOUT
TMRx OUTPUT
TMRx INPUT
tTIS
tTIH
tWH,tWL
tTOD
tHTO
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