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CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (
μ
PD78018F SUBSERIES)
(11)Notes on SBI mode
(a) Whether a slave is selected or not is detected by matching of a slave address that has been received
after the bus release signal has been issued (RELD = 1).
To detect matching of addresses, an address match interrupt (INTCSI0) that is generated when WUP =
1 is usually used. Therefore, detect whether a slave is selected or not by reception of a slave address
when WUP = 1.
(b) To detect whether a slave is selected or not when WUP = 0 without using the interrupt, do so by
transmitting/receiving a command set by program in advance, instead of using the address matching
method.
(c) In the SBI mode, output of the BUSY signal continues until the next serial clock (SCK0) falling edge after
a BUSY releasing command has been issued. If WUP = 1 during this period, BUSY cannot be released.
Therefore, to set WUP to 1, be sure to release the BUSY status, and make sure that the SB0 (SB1) pin
has gone high.
(d) Be sure to set the pin used to input or output data after the RESET signal has been input and before serial
transfer of the first byte.
<1>
<2>
<3>
Set 1 to the output latch of P25 and P26.
Set bit 0 (RELT) of the serial bus interface control register (SBIC) to 1.
Set 0 to the output latch of P25 and P26 to which 1 has been set.
(e) A positive transition of the SB0 (SB1) pin from low to high or high to low is recognized as a bus release
signal or a command signal when the SCK0 line is high. If the change timing of the bus is shifted due
to the influence of the board capacitance, data that is transmitted may be identified as bus release signal
(or a command signal) by mistake. Exercise care in wiring.